DP83869HM: Initialization issue

Hi, 
If you have MDIO register access, could you try reading register 0x19? LED polarity is set at the power-up based on strapping option. 

Have you also tried following this power sequence guideline on the datasheet?



Best,
J

Hi J,

Thanks for your response, 

Please find the checked details below,

Power sequence verified and attached below,


Readed startup register Values are below:

Reg- 0X0019: 4004
Reg- 0X01DF: 0044

seems like the results are ok, but still we are facing SFP initialization issue. Could you please let us know the next check point to proceed.

BR,
Mani

Hi Mani, 

When do you power VDD1P1?

Manigandan S said:

Reg- 0X0019: 4004
Reg- 0X01DF: 0044

It looks like the LED polarity is set correctly to active low based on your setting. If you would like to make it active high, please strap to GND instead of VDDIO. 

Manigandan S said:

seems like the results are ok, but still we are facing SFP initialization issue. Could you please let us know the next check point to proceed.

What exactly is the issue with SFP initalization?

Best,
J

Both the VDD1P1 and VDD2P5 is powering at the same time.

J Said: If you would like to make it active high, please strap to GND instead of VDDIO. 

Mani: Which LED strap pin will put in to Pull-down

J Said: What exactly is the issue with SFP initialization?

we have connected this SFP converter to KSZ9477 switch IC. We have tried to ping the KSZ switch IC via Fiber through SFP converter IC. But Ping is not happening and getting below message in command window,

If possible, we can connect a small sync-up short out the issue,

MailID: manigandans@iinvsys.com

BR,

Mani

Hi Mani, 

Manigandan S said:

Mani: Which LED strap pin will put in to Pull-down

The LED pins sample if the pin is strapped to GND or VDDIO and change their polarity based on the strapping as LED pins are also used as strappings for internal functions of the PHY. 
Below are the example configurations:

If you would like to keep the current strapping setting, you can write to bits 2, 6, 10 of the register 19h. 



And, currently, I do not seem to have enough information for a short sync-up.

Could you send us the register dump of C00h to C30h to have more idea of what is happening inside the fiber link with the PHY?
Could you also send us the schematic with the connection to the SFP cage?
Is this happening only on one PHY, or multiple PHYs?

Best,
J

Hi J,

I will try the Register write and read by later. for the moment please refer the below schematic for SFP cage connections

In our design we have two SFP converters, one is working consistently and another one is not working. Let me know your assist to proceed further.

Note: Both the SFP sections having same configurations.

BR,

Mani

Hi Mani, 

So there is two 869s separately connected to the different SFP converters, if I understand your comment correctly?
Is SFP2_RXLOS signal connected to 869?

Best,
J

Hi J,

Yes we have connected two different SFP to two different 869s. RXLOS signals connected to the 869s respectively.

BR,

Mani

Hi Mani, 

If that is the case, the register dump will be very helpful to see what is going on in the PHY. 
Could you verify that the Signal Detect Signal is reaching the PHY properly? If not, could you do ABA swap of the SFP module to see if works when the SFP module is swapped?

Best,
J