DS90UB954-Q1: CSI-2 Tx Port PASS not asserted

Hello,

Thanks for reaching out. Are you able to see valid data being output by the deserializer on a display or SoC? Can you update the register configuration so that register 0x21 = 0x81? If you read register 0x4E repeatedly, are the buffer errors consistently reported or do they clear after the first reads? The 0x4E register will keep the error bit set until it is read even if the error is no longer actively occurring.

Hi Darrah.  Thank you for your help.

Unfortunately I am still debugging that interface so I am not able receive MIPI video from the deserializer.

I did update register 0x21 = 0x81 but it had no effect.

Register 0x4E reads the same value when reads are repeated.

Dave

If buffer errors are reported on each read that means the errors are continuously occurring. A buffer error typically is due to data being sent to the deserializer faster than the device's CSI TX can output. However, you mentioned that increasing the TX speed by setting 0x1F = 0x00 has no effect, is that correct? The TX data output can also be increased by increasing the number of CSI lanes. For testing purposes, can you increase the number of CSI lanes from 2 to 4 by setting register 0x33 = 0x03? Replication mode will need to be disabled for this test since all four lanes will be used. So the register configuration will need to be updated to set register 0x21 = 0x01 as well.

Another test would be to use the serializer's pattern generator instead of the imager's data stream, and see if the same behavior is seen with the pattern. If you know the blanking details of the imager, the pattern generator can be programmed to match. Are you using the 953 serializer?

Hi Darrah.

I set FWD_CTL2 0x21 to 0x01, and also made sure that I was sequencing the enabling of the CSI-2 transmitter according to 7.4.28.1. I also set CSI_PLL_CTL 0x1f to 0x00 for 1.6 Gbps CSI TX speed.

I am no longer getting buffer errors and TX_PORT_PASS is now solidly asserted. All other RX and CSI status is indicating no errors.

However, I still do not get any signals (PASS, frame valid, line valid, etc.) when routing the CSI-2 TX Port to GPIOx Output Function (see Table 7-8).

Next step is to work on the Des to ISP MIPI interface.

Thank you for all of your help!

I'm glad that you were able to resolve the errors.

For the CSI-2 TX Port GPIOs, try updating the register writes so that the GPIOx_OUT_SRC = 110. So for example, if you wanted to output the OR PASS status, set the GPIOx register to 0x39.

That helped.  So mistake in datasheet?  Is there other errata that it would be important to be aware of?

Yes, this is a typo in the data sheet. The register functionality is intended to work with GPIOx_OUT_SRC = 110. There is no errata for the 954, but the GPIOx_OUT_SRC will be updated in the next revision of the data sheet.