DP83867IS: 4-level strap

Hi J-san,

Thanks for your reply.

Customer actually checked the timing when the hardware settings are reflected in the PHY.

As a result, the strap voltage is set immediately after RESET. Is this correct behavior?

Also, I set RX_D0, RX_D1, RX_D2, and RX_D3 to MODE4.

However, RX_D0 and RX_D1 are 0V, not 0.783V. RX_D2 and RX_D3 are about 0.7V.

Please tell me why RX_D0 and RX_D1 are 0V.

Best Regards,
Ishiwata

Hi Ishiwata-san, 

Shuji Ishiwata said:

As a result, the strap voltage is set immediately after RESET. Is this correct behavior?

This is the normal behavior as the datasheet specification does not specify minimum time when the strapping configurations will latch in. 

 

Shuji Ishiwata said:

However, RX_D0 and RX_D1 are 0V, not 0.783V. RX_D2 and RX_D3 are about 0.7V.

Please tell me why RX_D0 and RX_D1 are 0V.

After strap configurations are latched in, the voltages are meant to be dropped as these pins now will be used as an output pins. I have measured myself those pins on the EVM and I measured all RX_D pins drop to 0V in an idle state after the EVM powers up. 

Is the customer's PHY not strapping properly?

Best, 
J

Hi J-san,

Thank you for your answer.

Why is there a difference between RX_D1 and RX_D2?

Can I understand that near 0V is the correct operation?

Best Regards,
Ishiwata

Hi Ishiwata-san,

Near 0V is the correct operation if the PHY is in an idle state without the link. 

I am unsure why the customer sees difference voltage but it can happen if the PHY is transmitting data to the MAC.

I would need more information like the schematic to debug this further.

Best,

J

Hi J-san,

Thank you for your reply.

Regarding the issue where the strap voltage is around 0.7V, I received a circuit diagram from a customer,
so I will send the circuit diagram via private message,
so please let me know if there is anything you are concerned about.

I have an additional question about the timing when the strap is set.

You replied that the strap voltage drops because it is used as an output,
but judging from the waveform below, if the timing when the strap is reflected is immediately, won't it be 0V and MODE1?

Do you know the min and max values ​​that the strap is reflected at? Please let me know if you know roughly.

Best Regards,
Ishiwata

Hi Ishiwata-san, 

Shuji Ishiwata said:

Do you know the min and max values ​​that the strap is reflected at? Please let me know if you know roughly.

There is no minimum time, but the maximum time is 200ms. 

Looking at the schematic, it looks like the customer is using two PHYs. Is this behavior seen on both PHYs?
How frequently does this behavior happen?

In addition, what exactly is the problem that the customer is facing currently?

Comment about schematic: Because MDI side of the PHY has an inbuilt termination of 100 ohm, the customer doesn't have to put external resistors for 100 ohm differential termination. In addition, I noticed that the magnetics has turn ratio higher than our recommendation (2%) and has integrated center tap. We recommend customers to use magnetics that has separate center taps to GND like HX5008NL. For SGMII Mode 4 strap, TI recommends using Rhi = 4kΩ and Rlo = 10kΩ on RX_D0 and RX_D1 , RX_D2 and RX_D3.

Please let me know. 

Best,
J

Hi J-san,

Thank you for your reply.

In the data sheet below, the standard time for the strap setting to be reflected is 200 msec, but is it correct to understand that this is the maximum value?

The customer has not experienced any particular problems, but is concerned about the timing of the strap setting and has come to ask a question.

Thank you for checking the circuit diagram. I will provide feedback to the customer.

Best Regards,
Ishiwata

Hi Ishiwata-san, 

Yes, it is correct to understand that 200ms is the maximum value. 

Please let me know if the customer has any other questions. 

Best,
J

Hi J-san,

Thank you for your answer.

I have an additional question.
The waveform below is when it is set to MODE4, and the voltage rises slightly when RESET goes high.

In this case, it deviates from the TARGET VOLTAGE. However, the voltage will be higher than Max. I don't think it will be set to any other MODE, so is my understanding correct?

Best Regards,
Ishiwata

Hi J-san,

Thank you for your support.

I have an additional question.

(1)I have a question about the period in ①.
Please tell me the period during which Strap Configuration is completed.
Can I understand that it is set to the period shown below?
It is shorter than the 120nsec in the datasheet, but has it been set correctly?

(2)I have a question about period ②.
Can I understand that during this period, the strap configuration has already been completed and the pin function has been switched to another one?

Best Regards,
Ishiwata

Hi Ishiwata-san, 

The strap configuration is most likely set in 1. At which point during period 1 is unclear, however. 
My understanding is that the period 2 is low because the pin has been strapped and now is being used as otherwise. 

Best,
J

Hi J-san,

Thank you for your answer.

I have an additional question.

Customers are concerned that the MODE4 setting will be mistakenly set to other MODEx, such as the MODE3 setting.

In MODE4, there are settings of [Rhi=2.49kΩ,Rio=OPEN] and [Rhi=4kΩ,Rio=10kΩ].

The TARGET VOLTAGE is VDDIOx0.782 for the [Rhi=2.49kΩ,Rio=OPEN] setting and VDDIOx0.542 for the [Rhi=4kΩ,Rio=10kΩ] setting.

The TARGET VOLTAGE for MODE3 is VDDIOx0.255, which is close to the TARGET VOLTAGE for MODE4 [Rhi=4kΩ,Rio=10kΩ].

Are there any concerns that the MODE4 setting will be mistakenly set to other MODEx?

Best Regards,
Ishiwata

Hi Ishiwata-san,

There is no such concern as long as no other device is driving voltage on that line when the PHY resets.

Has the customer seen issue?

Best,
J

Hi J-san,

Thank you for your reply.

There was a request from a customer.

They asked that the setting of [Rhi=4kΩ, Rio=10kΩ] for MODE4 be included in the table.

They said that there is a possibility that it may be overlooked. Please consider this in the next revision of the data sheet.

Best Regards,
Ishiwata

Hi Ishiwata-san,

We will internally log this for the next revision.

Best,

J