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SN75DP130: Lane swap

Part Number: SN75DP130

Tool/software:

Dear Technical Support Team,

I'd like to lane swap.

For example,

Connect the source side LANE3± to the IN0± pins of the SN75DP130, and connect the OUT0± to the LANE3± on the sink side (DP connector).

According to previous post, It seems to be ok, however  should user set some register enable or disable for this comment "you must manually enable all the lanes for the device rather than having the DP130 detect which lanes to turn on."?  

If so, could you tell me  the steps and what register should change manually for lane swap?

SN75DP130: SN75DP130 DP Lane swap - Interface forum - Interface - TI E2E support forums

If this implementation guide has normal steps, I'd like to know what register should I change .

Implementation Guide: DP130 in a Sink

Regards,

ttd

  • ttd,

    Are you supporting DP++ or just DP?  For DP++, the DP130 has a different EQ setting for lane 3.  Lane 3 for DP++ is TMDS_CLK and the DP130 has a fixed 3dB of EQ for that lane. But if you are only supporting DP then all lanes are the same.

    If you are using the AUX snooping feature, then you have to use I2C to disable link training and manually enable all lanes when connecting lane 0 to IN3 of DP130.

    Thanks

    David

  • Hi David,

    Thank you for your reply.


    I believe that SN75DP130 automatically adjusts output level and input EQ adjustment from the Link Training command, but if Link Training is disabled for lane swap, do I need to manually adjust EQ and output level from I2C with monitorinig AUX SOOP?

    If the DP sink side is connected to various devices, is it easier to use the automatic adjustment by Link Training without lane swapping?

    Reagrds,

    ttd

  • Hi ttd,

    Is this a new design? If it is, is it possible to use DP141 linear re-driver instead the DP130 limited re-driver? You can swap the DP141 line order as long as the line order matches between the input and the output.

    I believe that SN75DP130 automatically adjusts output level and input EQ adjustment from the Link Training command, but if Link Training is disabled for lane swap, do I need to manually adjust EQ and output level from I2C with monitorinig AUX SOOP?

    Please refer to the table below, the EQ also depends on the EQ_I2C_ENABLE bit setting.

    Thanks

    David

  • Hi David,

    This is a new design. When swapping lanes, can I use link training without disable link training and enable all lanes like SN75DP130?

    Could you point out the explanation of lane swap on DP141 datasheet. I can't find it.

    Regards,

    ttd 

  • Hi ttd.

    The DP141 does not participate in the link training and all four lanes are always enabled. This is why I am wondering if the DP141 will be a better fit for this design.

    Thanks

    David