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DP83869HM: Datasheet timing table clarification

Part Number: DP83869HM

Tool/software:

Hi,

I am trying to prepare FPGA timing constraints in order to connect to DP83869HM PHY via RGMII interface. I am confused about the timing tables and diagrams provided in the datasheet. Therefore, I would like to ask your support for clarification.

I would like you to confirm my understanding is correct as below:

- Section 6.6: OUTPUT TIMING table corresponds to TX signals from PHY to FPGA.

- Section 6.6: RGMII INPUT TIMING table corresponds to RX signals from FPGA to PHY.

Section 6.7: Figure 6-6. RGMII Transmit Multiplexing and Timing Diagram corresponds to TX signals from PHY to FPGA.

Section 6.7: Figure 6-7. RGMII Receive Multiplexing and Timing Diagram corresponds to RX signals from FPGA to PHY.

Thanks in advance,

  • Hi, 

    - Section 6.6: OUTPUT TIMING table corresponds to TX signals from PHY to FPGA.



    If you are referring to this table, this means RX signals from the PHY to the FPGA (MAC). 


    - Section 6.6: RGMII INPUT TIMING table corresponds to RX signals from FPGA to PHY.

    This refers to TX signals from the FPGA to the PHY. 




    Section 6.7: Figure 6-6. RGMII Transmit Multiplexing and Timing Diagram corresponds to TX signals from PHY to FPGA.


    This refers to the TX signals from the FPGA to the PHY. 


    Section 6.7: Figure 6-7. RGMII Receive Multiplexing and Timing Diagram corresponds to RX signals from FPGA to PHY.


    This refers to the RX signals from the PHY to the FPGA. 

    These are because RGMII specification outlines the signal of the PHY from the MAC side. 

    Please let me know if you have any other questions. 

    Best,

    J

  • Why is there a mismatch in naming time intervals on the diagrams and in the tables?

  • Hi Andrei, 

    I apologize for the confusion. The team will take note of that and will fix it. 

    Best,
    J