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DS90UB954-Q1: AEQ status understanding (adaptive equalization status on FPDLinkIII)

Amotz kats
Prodigy 60 points

Part Number: DS90UB954-Q1

Tool/software:

Hi TI,

Please explain the values received on EQ_STATUS (AEQ_STATS register (addr 0xD3) bits 5:0).

What range is possible? valid? 

(If this is the EQ lock level i'd expect 4 bits (0-F), and if it is 2 steps lumped together then i'd expect 8 bits.)

We have a user claiming to read (sometimes) 0x27 with correlation to get lock failure when this number is obtained, is that possible?

thanks a lot,

amotz  

  • +1
    TI__Mastermind 28181 points

    Hi Amotz,

    Thanks for reaching out with this question. A good way to understand the EQ would be looking through the app note below.

    Margin Analysis Program (MAP) and strobe positions for DS90UB954-Q1 and 960-Q1

    Generally, higher EQ codes are correlated with a channel which has higher insertion loss. Higher EQ codes will equalize this channel for proper recovery of the forward channel frames at the FPD RX.

    In cases where lock is low, EQ generally has less meaning as the FPD RX has not locked. When the FPD RX is not locked, the EQ will continue to search for a stable value where errors are not occurring. An abnormal EQ value would be a symptom of the RX being unlocked rather than the cause of it assuming that the min/max EQ has not been limited.

    Best,

    Thomas

  • 0 in reply to Thomas Bejin
    Prodigy 60 points

    Thank you Thomas,

    In that case i understand that  AEQ_STATS[5:0] = {EQ2,EQ1} from table 4 inside the application note (snla301).

    If this is true, the case is closed.

    best regards,

    amotz