This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TIOL221: TIOL221 in pin mode

Part Number: TIOL221

Tool/software:

Hello!
We are using TIOL221 in pin mode and have encountered several issues that need to be confirmed. Please clarify them. Thank you.

1. We need to keep EN1 and EN2 in both high/low states. Can their pins be directly connected together to save wiring space? Supply 5V voltage to it through a 5k Ω pull-up resistor (when separated, 10k Ω should be used separately, equivalent to two resistors of the same specification connected in parallel) to ensure that it remains in a high level state?

2. As mentioned above, can the CS/PP and SPI/PIN pins be directly connected together? Connect a 5k Ω pull-down resistor (when separated, 10k Ω should be used separately, which is equivalent to two resistors of the same specification in parallel) to ground and keep it in a low level state?

3. When using the pin mode of TIOL221, some pins (RX1, V5IN, DI, RESET, RX2, WU, SDO/NFLT2, SCK) do not need to be used. Do we need to connect these pins through pull-up/pull-down resistors?

4. Is it appropriate to connect the VOUT pin of TIOL221 to ground through a 1uf capacitor?

5. The INT/NFLT1 pin outputs a high level during normal operation and a low level during output faults. So when the output is high, should it maintain a constant voltage source min (VOUT+0.3V, 6V) output, or a constant current source (-5mA, 5mA) output? Or is there a specific relationship between the output voltage and current of this pin? Furthermore, can the INT/NFLT1 pin be used as an analog output? If it is connected to the VOUT pin through a 10k Ω pull-up resistor, will the high resistance state of the pin be converted to a 5.3V voltage source output?
At the same time, the output current range of the INT/NFT L1 pin (-5mA, 5mA) means that the maximum current allowed to flow through it is 5mA, including the maximum current allowed to flow through it. That is, the maximum current allowed to flow from VOUT to the INT/NFT L1 pin is 5mA?


  • Hello Zhongshu,

    1. We need to keep EN1 and EN2 in both high/low states. Can their pins be directly connected together to save wiring space? Supply 5V voltage to it through a 5k Ω pull-up resistor (when separated, 10k Ω should be used separately, equivalent to two resistors of the same specification connected in parallel) to ensure that it remains in a high level state?

    Yes, you can connect the EN1 and EN2 pins together if you do not need to have independent control over the two channels.  Each pin has an internal 100kΩ pull-down resistor, so connecting these two pins together will make the combined internal pull-down resistance 50kΩ. 

    There is no set requirement for a particular pull-up resistor, so you can use whatever value you prefer to ensure the VIL and VIH voltage levels are achieved.  With a 5V supply, the VIL max is 1.5V, and VIH min is 3.5V.  After doing a quick calculation, a single pull-up resistor of <20kΩ is needed when both EN pins are connected together in order to achieve a VIH of 3.5V.

    2. As mentioned above, can the CS/PP and SPI/PIN pins be directly connected together? Connect a 5k Ω pull-down resistor (when separated, 10k Ω should be used separately, which is equivalent to two resistors of the same specification in parallel) to ground and keep it in a low level state?

    I'm not sure what your application is, but both the CS/PP and SPI/PIN pins are input pins and just need to be set to the appropriate voltage levels for your application. They could be tied together, but for pin mode the SPI/PIN needs to be low, which will mean CS/PP is also low.  This will restrict the CQ and DO Driver Mode to either PNP or NPN depending on the value of the SDI/NPN pin.

    3. When using the pin mode of TIOL221, some pins (RX1, V5IN, DI, RESET, RX2, WU, SDO/NFLT2, SCK) do not need to be used. Do we need to connect these pins through pull-up/pull-down resistors?

    RX1 and RX2 are output pins and can be left floating if unused.

    V5IN is optional and can be left floating if unused as mentioned in the datasheet.

    DI is an input pin as a general rule should not be left floating.  Generally the DI pin is directly connected to the DO pin with a trace so that DO and DI are always the same.

    RESET is an open-drain output pin and is generally pulled high to VOUT with a pull-up resistor.

    WU is an open-drain output pin and is generally pulled high to VOUT with a pull-up resistor.

    SDO/NFLT2 is an open-drain output pin (in pin mode) and is generally pulled high to VOUT with a pull-up resistor

    SCK is an input pin with an internal 100kΩ pull-down resistor, so it can be left floating if unused.

    4. Is it appropriate to connect the VOUT pin of TIOL221 to ground through a 1uf capacitor?

    Yes, a minimum 1uF capacitor is required between VOUT and LM (ground) to stabilize the LDO output voltage.  It is OK to use a larger capacitor, but a capacitor less than 1uF may cause regulation and stability issues with the LDO output voltage.

    5. The INT/NFLT1 pin outputs a high level during normal operation and a low level during output faults. So when the output is high, should it maintain a constant voltage source min (VOUT+0.3V, 6V) output, or a constant current source (-5mA, 5mA) output? Or is there a specific relationship between the output voltage and current of this pin? Furthermore, can the INT/NFLT1 pin be used as an analog output? If it is connected to the VOUT pin through a 10k Ω pull-up resistor, will the high resistance state of the pin be converted to a 5.3V voltage source output?
    At the same time, the output current range of the INT/NFT L1 pin (-5mA, 5mA) means that the maximum current allowed to flow through it is 5mA, including the maximum current allowed to flow through it. That is, the maximum current allowed to flow from VOUT to the INT/NFT L1 pin is 5mA?

    In Pin mode the INT/NFLT1 is an open-drain output pin that requires an external pull-up resistor to VOUT for a "High."  The pin will only sink current when it is in the active Low state where it is sinking current through the pull-up resistor to create a low voltage on the pin.  But to the question, it would be more associated with a constant current and the device would transition between not sinking current in the High state, and sinking current in the low state.

    In SPI mode the INT/NFLT1 is a driven output pin and will output a voltage between VOUT-0.5V and VOUT in the High state, and 0V and 0.4V in the Low state.

    Yes -5mA to 5mA is the max level of current allowed to flow through the pin when operating as a driven output pin.  External pull-up resistors should be sized such that they do not cause more than 5mA of current to flow when operating as an open-drain. (V=I*R)

    Regards,

    Jonathan

  • Hi Jonathan,

    The RESET, WU, and SDO/NFLT2 pins need to be connected to VOUT through pull-up resistors. I would like to ask, can these three pins be combined together? Connect them to VOUT through a pull-up resistor? If so, what value should the resistor be set to?

    Thanks

    Lillian 

  • Hi Lillian,

    Perhaps I wasn't clear.  These pins are not "required" to be connected to VOUT through pull-up resistors, but they generally are connected to a resistor. 

    It is generally safe to leave open-drain output pins floating if they are not used, but they can pick up static voltage and charge without being tied to a static voltage. 

    I don't have a recommendation on a value should you use to combine the pins to a single resistor since it would only be used to tie off the pins and not to establish valid logic High/Low voltage levels which would be required if they are used.

    Regards,

    Jonathan