DP83TC814S-Q1: Master/Slave test

Hi Ivy,

Ivy Jin said:

1. As the following figure says: "Master/Slave are configured using either hardware bootstraps or through register access." Does this mean that a hardware circuit configuration or a software register configuration can be selected? 

You can choose a hardware configuration and override it using the register configuration. However, once the device uses the software configuration it maintains that configuration because the hardware configuration is overridden. Unless you resample the pin straps by resetting the PHY using the Reset_N pin.

Ivy Jin said:

a. So if the hardware circuit is configured as Slave (SM keep floating), can it still be configured as Master via software? 

yes and yes to the next one.

Ivy Jin said:

c. So if the hardware circuit is configured as Slave (SM pull up), can it still be configured as Master via software? 

When SM is pulled up (By SM I assume you mean LED_0) the configuration is Master by hardware. But yeah, you can configure it to be Master via software too.

Ivy Jin said:

2. If the software is configured with the above mode at initialization, how can we confirm that the configuration was successful? Or what registers can read back? 

Read 0x1834

8001 means slave

C001 means master

Ivy Jin said:

b. For Test mode0\1\2\4\5, how do the read the confirmation status? 

What do you mean by this?

Ivy Jin said:

 In TDR Testing Procedure, is Step 1(Write Reg.[0x1834] = 0x8001) mandatory regardless of Master/Slave mode?

By setting the device to slave mode you are clearing the line for TDR testing. The link must be down. It is necessary to configure the device as a slave if the device that's doing the TDR is configured as a master using hardware or software.

Ivy Jin said:

After Step1, they need to wait for more than 1s for Step2(TDR configuration: Pre-run) register write? 

No need to wait. https://www.ti.com/lit/an/snla389e/snla389e.pdf

Good luck in your design!

Best regards,

Nick

Hi Nick,

Thanks for your comments!

Nick Peabody said:

b. For Test mode0\1\2\4\5, how do the read the confirmation status? 

What do you mean by this?

The problem is, for Test mode0, Test mode1, Test mode2, Test mode4, Test mode5, How to confirm that the configuration was successful and that the mode is currently in?

Regards,

Ivy

Hi Ivy,

Not a problem.

In each test mode, the PHY is supposed to generate patterns on MDI lines or expose internal clock signal on a pin for measurement of different electrical parameters. You can measure the output to verify,

https://download.tek.com/datasheet/TekExpress-Automotive-Ethernet-1000BASE-T1-100BASE-T1-MSO6-Datasheet-61W614083.pdf

Check the above out.

Best regards,

Nick

Hi Nick，

The customer has configured the hardware pin floated and wants to set the PHY to Master mode via software configuration, according to Table 3-1, Master Mode Configuration section. But it was unsuccessful. May I ask the potential reasons?

After the software initializes the Master parameters, read 0x1834 and display 8000. 

Regards,

Ivy

Hi Ivy,

Register 0x1834 is an extended register, which must follow extended register space access. Please see below.

Write:

000D 0001
000E 0834
000D 4001
000E C000

Read back:

000D 0001
000E 0834
000D 4001
000E

Let me know if this is able to provide the correct readback value. 

Thanks,

David

Hi David, Nick,

The customer performed the TDR testing in accordance with the 7-1. TDR Run Procedure section. After performing Step1 - Step4, when performing Step5, The value read from 0x001E is 0.

Because after performing the Step 2 TDR configuration: Pre-run and Step 3, they read back all the registers in the following figure and found that the values of the registers are correct except for the registers in the red box. The register values in the red box are all 0 

Therefore, Step 5 can not read [1,0] and Step 6 can not read properly. 

May I know if the value read from 0x001E is 0, which indicates that there is noise on the actual line or that the TDR Testing is configured incorrectly? 

Q1: If it is caused by noise, what is the general cause? How to improve and suppress noise?

Q2: If it is a configuration issue, how should it operate correctly? (Step 1: Wait for about 1 s after register write./Step 4: Wait for 100 ms. The delay for the two steps are also set by the customer )

Regards,

Ivy

Hi Ivy,

If Register 0x1E is 0, the TDR did not start. Bit[1] should show 1 when TDR is ran.

Please check that the extended register access procedure given in section 8.4.9 of the datasheet is being followed. 

See also attached script, please check your configuration.

// Title: DP83TC812 TDR Test
// Description: Run TDR Test. See SNLA389 for more info. 
// Texas Instruments USB-2-MDIO


//**NOTE: Link partner must be silent before starting TDR test. Set link partner to slave mode prior to running.

begin

000D 0001
000E 0834
000D 4001
000E 8000

0523 0001
0827 4800
0301 1701
0303 023D
0305 0015
0831 3003
001F 4000
0523 0000
001F 0000

001E 8000
001E
001E
001E		//Extra reads added as time for TDR to converge (100ms). 0x001E[1:0] = [TDR done : TDR fail] 
0310		//See SNLA389 for interpretation of 0x310 value.

end

Thanks,

David

Hi David,

Thanks for your comments.

The previous read back value of 0x001E was 0, probably because the TDR did not start.
Now the customer has successfully started TDR because the readback value of 0x001E is not 0.

The customer still has two questions.

Q1: Is 0x001E[1:0] = [TDR done: TDR fail] readback 2 when only the cable is shorted or open? The readback value is 3 when the cable is connected properly.

Q2: When testing short to ground or short to power, TRD_P or TRD_N is abnormal only at the moment of contact with the ground or power supply, and then it's back to normal.  (The customer‘s operation is to connect the TRD_P or TRD_N pins directly on the ground or power source)

Is this a normal phenomenon?

However, when TRD_P and TRD_N are shorted, they remain in an abnormal state and the SHORT reply of 0x310 can be read.

Regards,

Ivy

Hi Ivy,

David is out of the office today and will get back to you tomorrow.

Best,

Evan Su

Hi Ivy,

Q1: Register 0x1E = 0x0002 indicates a successful run of TDR. A value of 0x3 indicates that the TDR failed. This will happen if the link partner is still connected and transmitting signal. 

Q2: What do you mean by "TRD_P or TRD_N is abnormal" and "and then it's back to normal"?

Thanks,

David