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DP83TC812S-Q1: Link Down issue

Daniel Wang (auto)
Expert 3570 points
Part Number: DP83TC812S-Q1

Tool/software:

Hello team,

My customer is working on the PHY bring-up of DP83TC812S PHY chip.
The intended configuration for PHY is as below,

Mode – Master

Speed – 100 Mbit

MII mode – SGMII

The bootstrap pin configuration is as below.

Currently, it is observed that PHY is not in Link up state.
The link partner is configured as Master/Slave auto configuration at 100 Mb.



Register dump as per troubleshooting guide.

DP83TC812S BootStrap Config.xlsxDP83TC812S_RegDump.xlsx
Please take a look and let us know the root cause for this issue.

Thanks

Regards,

Daniel Wang

  • 0
    TI__Mastermind 18950 points

    Hi Daniel,

    I am looking over the schematic and register dump and will let you know my feedback soon. I have some questions:

    • Is it possible to force the partner PHY into Slave mode to reduce the chances that a problem is happening with its master/slave auto configuration?
    • What is the model of the partner PHY?
    • Besides the hardware bootstraps, has the DP83TC812 been configured with the Master mode script in our SNLA389E application note (https://www.ti.com/lit/an/snla389e/snla389e.pdf)?
      •  If this configuration is not applied, there is a higher chance of interoperability issues with PHYs from other vendors.

    Best,

    Evan Su