Part Number: DP83867IR
Tool/software:
Hello everyone,
i'm struggling with a problem on a Custom Board.
I have a zynq ultrascale+ mpsoc XCZU9EG-2FFVB1156I and i have an Ethernet connection RJ45 through PHY DP83867IRPAPT. I'm using HX5008NL as magnetic.
For the DP83867 i've setted by strap configuration Auto-Negotiation "Enabled" (RX_CTRL MODE 3, Pull-down resistance = 2.49kOhm ,Pull-up resistance = 5.76kOhm), other strap pins have no pull-up/pull-down resistances (i assume they are in MODE 0). I'm in RGMII Mode to GEM1 of PS Side of the Zynq. I have a Clock oscillator @25MHz (i've checked the presence by an oscilloscope) and i have two LEDs connected to LED0 and LED1 (pin 62 and 61).
I run the lwIP Xilinx example in Vitis and i havethis problem:
During auto negotiation phase it returns Autonegotiation failed, PHY setup error. To bypass this problem, i have to modify network board properties on my PC and i have to set the field " Speed and Duplex" to 1.0 Gbps, or 10 Mbps Full Duplex. If i set 100 Mbps Full Duplex Autonegotiation still has an error.
With these settings 90% of times autonegotiation pass (at 10Mbps and 1Gpbs) but some times still gives an error. At 100Mbps always gives an error.
Why have i to set manually the speed to pass autonegotiation phase?
And why at 10Mbps and 1.0Gbps autonegotiation phase is mostly succesfull and at 100 Mbps has never returned succesfully?
Thanks in advance,
Andrea
