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DP83TG720-EVM-AM2: The ethernet phy fails to respond over mdio lines

Dhananjay Sutariya
Prodigy 10 points
Part Number: DP83TG720-EVM-AM2

Tool/software:

Hi Team,
Currently im trying to interface a dp83tg720 chipset on imx8qm.
Setup Details are as follows:
Kernel: 6.6.23 (nxp-imx) bsp
EVK: Imx8QM with one ehernet connected .
Driver: https://github.com/nxp-imx/linux-imx/blob/lf-6.12.y/drivers/net/phy/dp83tg720.c

I have made the BSP changes for RGMI2 interface.
The Mdio lines are shared between both the Phy's. (One is internal phy connected on EVK)


The device probe fails with the log:
[    2.968110] mdio_bus 5b040000.ethernet-1: MDIO device at address 12 is missing.

We are able to observe the following:
1) All the power supplies: VDDIO_1V8,1V0,3V3 proper.
2) Crystal frequency getting 25 Mhz.
3) MDC frequency 2.5Mhz.
4) MDIO are getting observed with NACK.
5) Reset we are able to observe.

Using phytool im able to get the output of the phy connected over 0th address.
However for Address 12 we are observing FFFFFFF response.

Regards,
Dhananjay Sutariya

  • 0
    TI__Mastermind 18950 points

    Hi Dhananjay,

    I see the IMX8QM is a NXP processor board, which I haven't worked with before. I have some questions about the configuration and environment of the DP83TG720 before I can assess debug steps:

    • This thread is posted under the DP83TG720-EVM-AM2 product, which is a specific TI evaluation module. Can you confirm if you are using the DP83TG720-EVM-AM2, or is the DP83TG720 device installed on another type of board?
    • Are we certain that Address 12 corresponds to the DP83TG720? I have not used phytool before and am not sure how the devices are identified and how the addresses are assigned.
    • Did I understand correctly that the other PHY that is sharing the MDIO line with the DP83TG720 does not have communication issues?

    Best,

    Evan Su

  • 0 in reply to Evan Su
    Prodigy 10 points

    Hi Evan,
    Thank you for your response, please find my response below:

    1) This thread is posted under the DP83TG720-EVM-AM2 product, which is a specific TI evaluation module. Can you confirm if you are using the DP83TG720-EVM-AM2, or is the DP83TG720 device installed on another type of board?

    [Dhananjay Response]Yes we are using the DP83TG720-EVM-AM2 EVK.

     

    2) Are we certain that Address 12 corresponds to the DP83TG720? I have not used phytool before and am not sure how the devices are identified and how the addresses are assigned.

    [Dhananjay Response]Yes we have configured the address using hardware settings.

     

    3) Did I understand correctly that the other PHY that is sharing the MDIO line with the DP83TG720 does not have communication issues.

    [Dhananjay Response]Yes this is correct. Randomly the other phy which is already connected within the EVK stops getting the ip address.
    After this we plugout the DP83tg720 and restart the board to find that everything is working okay.


    Regards,
    Dhananjay

  • 0 in reply to Dhananjay Sutariya
    TI__Mastermind 18950 points

    Hi Dhananjay,

    Dhananjay Sutariya said:
    [Dhananjay Response]Yes we are using the DP83TG720-EVM-AM2 EVK.

    Thanks for clarifying. I reviewed the User's Guide for the DP83TG720-EVM-AM2 (https://www.ti.com/lit/ug/spruja9a/spruja9a.pdf) and have some ideas:

    • Page 6 lists the DF40GB header pinout. This header contains all the important MAC data and supporting signals is intended to be connected to a TI Sitara AM2x EVM.
      • What method are you using to connect the signals in this header? Is it being plugged directly into some kind of baseboard containing the IMX8Q or have you manually wired the signals out with a breakout?
      • Are all signals in the table connected as expected, or are any missing?
    • Page 7 lists the test points. Can you probe the following signals while the board is on to get a better idea of the situation?
      • TP10 (CLK_OUT2) - see if there is a 25 MHz clock signal
      • TP22 (MDIO_MDIO) - check the DC voltage of the line when no data is transmitted

    I am thinking there could be an unusual configuration issue with the DP83TG720, and/or there could be an unusual condition on the MDIO line. Since the DP83TG720-EVM-AM2 isn't originally intended for use with boards and systems from non-TI vendors, I want to investigate the hardware interface.

    Best,

    Evan Su

  • 0 in reply to Evan Su
    Prodigy 10 points

    Hi Evan,

    Thank you for your response earlier.

    Input from our hardware team:

    Can we connect the rgmi lines directly over 3v3 volts as we have a Ethernet chip sharing same mdio lines working with 3ve however for the dp83 we need to use level shifter to covert voltage levels to 1v8 levels.

    Will connecting 3v3 damage the dp83 chipset?

    Regards,

    dhananjay

  • 0 in reply to Dhananjay Sutariya
    Prodigy 10 points

    Hi Evan,

    Shedding clarity on my earlier response:
    We are connecting MDIO with NXP EVK 3V3 MDIO voltage directly, sometimes device is detected at address sometime its not.

    Also 1V8 MDIO facing issue detection issue persistently.
    INH and Wake pin is float condition



    Regards,
    Dhananjay 

  • 0 in reply to Dhananjay Sutariya
    Prodigy 10 points

    continuing on this:
    Reset controlled by NXP imx8qm. 

  • 0 in reply to Dhananjay Sutariya
    TI__Mastermind 18950 points

    Hi Dhananjay,

    Dhananjay Sutariya said:
    Can we connect the rgmi lines directly over 3v3 volts as we have a Ethernet chip sharing same mdio lines working with 3ve however for the dp83 we need to use level shifter to covert voltage levels to 1v8 levels.

    Sorry, could you clarify if your hardware team is talking about the RGMII lines or about the MDIO/MDC lines?

    On the DP83TG720 device, the MDIO/MDC pins operate on the VDDIO voltage domain, which could vary from 1.8 V to 3.3 V depending on the board. The absolute maximum rating for MDIO is VDDIO + 0.3 V according to the table in section 6.1. So if the DP83TG720 VDDIO is 1.8 V, I would not recommend connecting it to other devices with 3.3 V logic levels.

    Best,

    Evan Su