Tool/software:
Hi,
We are communicating using FPDLink III with the DS90UB948 and DS90UB927. The datasheet states that the MAP determines LOCK (= error) using 3 bits for DAC, CLOCK1, and CLOCK2.
1) Is the image in the attached diagram correct?
If it is correct, then the MAP cannot ensure sufficient quality, so we will also conduct eye pattern and BER tests.
2) Where are the bits for DAC, CLOCK1, and CLOCK2 located within the 35 bits? Is there data available for the bit allocation?
Best,