SN65DSI84: DSI Tuner debug issues

Hi Alan,

Alan Xia said:

1. In the DSI-Tuner documentation example, why are the LVDS timing and DSI timing settings different? See the figure below.
How do I set these two?

Can you please share the document they were using? Was it a previous version?

Please use this User Manual for reference: https://www.ti.com/lit/an/slla332b/slla332b.pdf

Video guide: https://www.ti.com/video/5829462797001

Alan Xia said:

2. After installing the DSI-Tuner tool, the interface is different from that in the document (the left picture below is the document picture, and the right picture is the newly installed interface). The clk in the red box in the picture below cannot be set;
How to solve it?

Use the zip file in this E2E to download: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/850530/sn65dsi84-q1-need-sn65dsi84-q1-dsi-tuner-tool

Please use this link and install. Does the issue still occur?

Alan Xia said:

3. What do the parameters in the red box in the figure below mean? How should they be set to ensure that the parameter requirements are met?

These are output settings, and not inputs that can be set. The line time is the time between Hsync to Hsync. These details are shared in the User Manual SLLA332B.

Let us know if the questions are resolved. We would suggest to use Test Pattern for first test to verify the LVDS outputs.

Best regards,
Ikram

Hi Ikram，

My computer has a problem that makes it impossible to open Java applications. This is caused by computer permissions and compatibility issues. I cannot help customers configure this parameter. I asked other colleagues to open the compressed package. After installation, there was no problem with the configuration interface. It was probably a software or environment problem.
The customer's problem is probably also an environmental problem that caused compatibility issues in the DSI Tuner interface.
Therefore, I have to trouble you to help configure the following parameters and export a CSR file. Thank you for your support.

The customer has a swap design:

timing as below：

Hi Alan,

Please check whether these inputs match your requirements:
- LVDS timings
- Hsync, Vsync and DE polarity
- DSI settings (LP, Burst mode, sync mode)
- DSI or REFCLK used


If the DSI or LVDS settings used are different, then we would need to generate new initialization script accordingly.

LVDS timings and configuration



DSI settings



Outputs:



CSR for test pattern:

//=====================================================================
// Filename   : CSR_0618_test_pattern.txt
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
//=====================================================================
0x09              0x00
0x0A              0x04
0x0B              0x00
0x0D              0x00
0x10              0x26
0x11              0x00
0x12              0x28
0x13              0x00
0x18              0x6c
0x19              0x00
0x1A              0x03
0x1B              0x00
0x20              0xc0
0x21              0x03
0x22              0x00
0x23              0x00
0x24              0x38
0x25              0x04
0x26              0x00
0x27              0x00
0x28              0x20
0x29              0x00
0x2A              0x00
0x2B              0x00
0x2C              0x12
0x2D              0x00
0x2E              0x00
0x2F              0x00
0x30              0x02
0x31              0x00
0x32              0x00
0x33              0x00
0x34              0x12
0x35              0x00
0x36              0x08
0x37              0x00
0x38              0x13
0x39              0x00
0x3A              0x22
0x3B              0x00
0x3C              0x10
0x3D              0x00
0x3E              0x00


The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

//=====================================================================
// Filename   : CSR_0618_DSI84.txt
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
//=====================================================================
0x09              0x00
0x0A              0x04
0x0B              0x00
0x0D              0x00
0x10              0x26
0x11              0x00
0x12              0x28
0x13              0x00
0x18              0x6c
0x19              0x00
0x1A              0x03
0x1B              0x00
0x20              0x80
0x21              0x07
0x22              0x00
0x23              0x00
0x24              0x00
0x25              0x00
0x26              0x00
0x27              0x00
0x28              0x20
0x29              0x00
0x2A              0x00
0x2B              0x00
0x2C              0x12
0x2D              0x00
0x2E              0x00
0x2F              0x00
0x30              0x02
0x31              0x00
0x32              0x00
0x33              0x00
0x34              0x12
0x35              0x00
0x36              0x00
0x37              0x00
0x38              0x00
0x39              0x00
0x3A              0x00
0x3B              0x00
0x3C              0x00
0x3D              0x00
0x3E              0x00


The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

Hi Ikram，

Thank you very much for your professional help.
Regarding step 9, please confirm and give feedback on the following questions, thank you

After initialization is completed, read back all configuration register values ​​to confirm; if the read back finds that the register value is incorrect, do you need to start from step 2 and re-initialize?

Hi Alan, if register value is incorrect then yes the customer should write the CSR registers again. This is an added step to check the values.

Best regards,
Ikram

Hi Ikram，

There is no relevant register configuration for the following DSI mode in the script. The DSI working mode of 65DSI84 should be adaptive according to the SOC DSI mode, right?

Hi Alan,

The DSI settings need to be programmed. Please ask the customer about the DSI configurations they are using, and the DSI84 should be programmed to match the input.

Best regards,
Ikram

Hi Ikram，

Pls help to confirm：

1. The configuration script generated by the customer according to the following configuration also does not have the corresponding register. Is it configured on the SOC side or does it need to be manually configured on the DSI84?

2. What do the following options mean? Which one should I choose?

Hi Alan, I will check this and get back to you soon.

Thank you,
Ikram

Hi Ikram，

Thanks for your help！ Looking forward to your help.

Hi Alan,

Alan Xia said:

2. What do the following options mean? Which one should I choose?

We checked with the DSI Tuner, and the DSI section drop downs (LP, Burst mode, Sync mode) are informational only. So it's only for information and does not change the script.

Did the test pattern script we shared earlier work when tested?

- Ikram

Hi Ikram，

According to the LVDS requirements of the screen, the LVDS output voltage of the currently generated configuration script is too low. Do we need to increase it by one level?
Are there any design suggestions for this output amplitude? 200mV is too low. I am worried that it will affect the high and low temperature stability and EMC interference immunity.

Hi Alan,

It's shared in the datasheet specifications 6.5 Electrical Characteristics "FLATLINK LVDS OUTPUT" section that the steady-state differential output voltage |VOD| can be changes using 0x19 register. 



You can write to the 0x19 register to set as needed, based on the voltage swing level required for the panel, based on the termination (100 Ohm or 200 ohm). If the panel requires 350 mV typical, then you can set the 0x19 register accordingly to a setting close to those levels.

Best regards,
Ikram