TMDS1204: HDMI Redriver Validation

Hi Shifali,

TMDS1204 has been used with multiple SOCs over the years.

Best,

J

Hi J,

Our target SoC is the Zynq UltraScale+ XC7ZEV. Have you validated this redriver chipset with this SoC?

Thanks,

Shifali

Hi Shifali, 

As long as the SOC supports HDMI 2.1 at 12G, TMDS1204 should be able to support it. 

Best,
J

Hi J,

Whether TMDS1204 IC has any power sequence requirement.

Thanks,

Shifali N

Hi Shifali,

There is no recommended power sequence for TMDS1204.

Best,

J

Hi J,

What is the acceptable propagation delay for HDMI 2.1 signals.

Thanks,

Shifali

Hi Shifali, 

HDMI 2.1 does not have a defined propagation delay. For TDP1204, it will equalize whatever signal it receives so it wouldn't matter how/when TDP1204 receives the HDMI signal as long as HPD is high. 

Best,
J

Hi J,

HDMI signals are typically group length-matched. In earlier versions, the three data lines were length-matched with the clock to avoid skew caused by mismatch. However, in HDMI 2.1, the clock is embedded within the data stream.

I have a few queries regarding HDMI 2.1:

1. Could you please confirm whether group length matching is still required for HDMI 2.1 signals?

2. In HDMI 2.1, which data line carries the embedded clock?

3. What is the maximum allowed trace length for HDMI 2.1 signals?

Thanks,

Shifali N

Hi Shifali, 

Shifali N said:

1. Could you please confirm whether group length matching is still required for HDMI 2.1 signals?

Yes, this is recommended within 50 mils. 

Shifali N said:

2. In HDMI 2.1, which data line carries the embedded clock?

All four lanes. 

Shifali N said:

3. What is the maximum allowed trace length for HDMI 2.1 signals?

This will depend on how much insertion loss is on the board and its material. Please use the datasheet and the board material's insertion loss to calculate the maximum trace length that TMDS1204 can support. 

Best,
J