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DP83867E: xGMII Interrupt Error

Elmar Bernhardt
Prodigy 10 points
Part Number: DP83867E

Tool/software:

Dear all, 

We are currently debugging a Cyclon V FPGA (commercial Ethernet IP block) design with two Dp83867E Ethernet Transceiver.

The issue is an xGMII Error interrupt, which prevents testing with the IC's internal loopback functions between the PHU and the FPGA itself.

At 10MBits we get data transmitted out to the physical layer, but not at higher speeds. 

Clocks are stable and precise, within specs. Checked at XI and XO.

FPGA - dp83867e RX/TX trace lengths are well within delay specs, less than 0.256mm length difference.

After a reset of the xGMII error it reappears instantly.  

Any good suggestions on how to interpret the xRGMII error interrupt?

  • 0
    Prodigy 10 points

    Additional info: Link negotiation with PC is successful on all speeds, Speed indicator LEDs to 1000Mbit. All Status registers show no error. Except for the xGMII error interrupt. 

  • 0 in reply to Elmar Bernhardt
    TI__Mastermind 39855 points

    Hello,

    It is unsure why xGMII error would appear at the moment. Could you look to provide a register dump of 0x0-0x1F, as well as 0x6E and 0x6F?

    I assume you are using RGMII, correct? Would you be able to provide Reg 0x32 and 0x86 as well?

    I believe the interrupt error is preventing your code from testing loopback, as this would just be a simple status on the PHY. Is there a way to bypass this on your application to troubleshoot the MAC interface with MAC loopback (Reg 0x0[14])?

    Is this happening on both PHYs or only one? This could help rule out location-specific issues.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 10 points

    Hi Gerome, 

    Thank you for your quick reply. Sorry we had some public holidays, that's why our late response! 

    Please find answers to your questions below:

    • there a way to bypass this on your application to troubleshoot the MAC interface with MAC loopback (Reg 0x0[14])?

    In MAC loopback – both receiving and transmitting of packages is working.

    In MII loopback – Speed 10 is working, 100/1000 not

     

    Is this happening on both PHYs or only one?

    Both

    Can you identify an issue we don't recognize?

    Appreciate your help!

    BR Elmar

    ETH0 interface

    ETH1 interface

  • 0 in reply to Elmar Bernhardt
    TI__Mastermind 39855 points

    Hi Elmar,

    I see that no RX_ERs (Reg 0x15) is toggling which indicates that MDI is all clear.

    When implementing MII loopback, are you making sure to adjust Reg 0x0 to showcase appropriate speed on RX? RGMII clock bus is set depending on speed; 2.5MHz for no link/10M, 25MHz for 100M, and 125MHz DDR for 1G. 

    If you are, this could be indicative of unoptimial trace length on MAC interface.

    Could you also please differentiate your results of MAC loopback vs MII loopback?

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 10 points

    Hi Gerome, 

    So, it does look like we might have a problem with the FPGA SW tool, by chance we got the 1000Mbit running with MII loopback, so obviously the PHY works. PCB trace lengths etc. are OK. I will put an update, when the root cause is confirmed. 

    Thank you once more for your fast support!

    BR Elmar