• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 103 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867E: How to specify embedded clock for the SGMII-interface, instead of the parallel clock?

Jaidev Kaniyil
Prodigy 60 points
Part Number: DP83867E

Tool/software:

The DP83867E SGMII EVM evaluation-board has an SGMII-interface consisting of one transmit differential lane, one receive differential lane and one clock differential lane. I would like to remove the differential lanes for the clock so that the SGMII-Interface will embed the clock in the data-streams.  How could I achieve this configuration?  Please let me know which all registers of DP83867E have to be modified and what are the modifications,

Regards,

Jaidev

  • 0
    TI__Guru**** 177301 points

    Jaidev

    DP83867 SGMII interface is capable of working as a 4-wire or 6-wire SGMII interface. Register 0xD3 controls the SGMII configuration either as a 4-wire (without differential clock) or 6-wire (with differential clock). The default SGMII connection is through 4-wire.

     

    Thanks

    David