We are using a TI TSB81BA3E Phy with Xilinx Spartan 3E FPGA. The link layer is composed firmware (Micro Blaze)/gateware (CamBlink) on the FPGA.
In a three node configuration a few bus resets occur and the PC becomes the root and the bus is stable. In a two node configuration our board becomes the root. This occurs, before the peripherals become active on the FPGA/Firmware. We are assuming the phy is making this decision, before the firmware/gateware is active.
Reading the phy registers on our board as soon as the FPGA peripherals are enabled indicates that the the root bit is set, the root hold bit is not set, the gap counter is max (3F), the contender bit is not set and there are no set bits for the interrupts.
The windows driver should reset the bus, if it determines that the root is not a cycle master. We are not a cycle master. We may not be getting to that point, since we have observed on a forced root (to our board) that our board resets on a read request from the PC. Sometimes this results in a reset storm, but usually a several second reset.
The question is why would the phy on our board continue to be set as root? We are able to observe that the PC has the contender bit set so it should try to become root?
