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DS160PR410: Random Lane Failure During Operation – Request for Analysis

Kelley Kim
Prodigy 90 points
Part Number: DS160PR410


Tool/software:

Dear,

We're currently facing a critical issue involving the DS160PR410RNQR.

Below are the detailed observations and background.

Issue Summary

- Failure Rage : Approximately 20~40% during initial setup and operation

- Behavior :

>The device operates normally at first but fails after a certain period of runtime.

> I2C communication is stable and accessible even during the failure.

>One of the image lanes stops functioning (e.g., Lane2) randomly (refer to attached image1)

>The failed lane only recovers when the IC is physically replaced.

>Reattaching the previously failed IC reproduces the same failure. 

-The circuit was designed based on the reference schematic in TI's datasheet. (refer to attached image2)

  • 0
    TI__Genius 11940 points

    Hi Kelley,

    Does this occur on multiple boards or a single board?

    Does the same lane fail on all boards/devices, does one lane fail more frequently?

    How long is the device functional before a failure occurs?

    Can you confirm the Exposed Pad is connected to GND (Shown as pin 41 in schematics)?

    I will send a separate request to provide full schematics and layout if possible.

    Regards,

    Undrea

  • 0 in reply to Undrea Fields
    Prodigy 90 points

    Okay, I'll check the additional checking list.

    Also, would you please let me know the ESD protection ?

    Attached screen shot is the only ESD-related statement in the datasheet.

    1) Does this simply describe the production environment or does it mean the device is safely operate under those ESD conditions wihout any issues?

    2) Could you confirm whether there are any internal ESD protection circuits implemented in the DS160PR410, even if they are not described in the datasheet?

     

  • 0 in reply to Kelley Kim
    Prodigy 90 points

    Does this occur on multiple boards or a single board? -> It occurs on random board, and the occurrence timing is also random.

    Does the same lane fail on all boards/devices, does one lane fail more frequently? ->We're currently using only 2 lanes, the failure occurs randomly on either lane.

    How long is the device functional before a failure occurs? ->In some cases, it appears within 1 hour, normally operate for up to 2days before a failure occurs.

    Can you confirm the Exposed Pad is connected to GND (Shown as pin 41 in schematics)? ->Yes, we have confirmed the GND PAD is properly connected.

    We also checked for any signs of cold soldering but there's no anomalies at the exposed pad connection point. 

  • 0 in reply to Kelley Kim
    TI__Genius 11940 points

    Hi Kelley,

    The ESD ratings in the datasheet are the limits to which the device will continue to operate normally.  

    Internally, there is ESD protection implemented in the design.

    Regards,

    Undrea

  • 0 in reply to Undrea Fields
    Prodigy 90 points

    Dear, 

    Thank you for your explanation.

    How about my below answers? 

    Does this occur on multiple boards or a single board? -> It occurs on random board, and the occurrence timing is also random.

    Does the same lane fail on all boards/devices, does one lane fail more frequently? ->We're currently using only 2 lanes, the failure occurs randomly on either lane.

    How long is the device functional before a failure occurs? ->In some cases, it appears within 1 hour, normally operate for up to 2days before a failure occurs.

    Can you confirm the Exposed Pad is connected to GND (Shown as pin 41 in schematics)? ->Yes, we have confirmed the GND PAD is properly connected.

    We also checked for any signs of cold soldering but there's no anomalies at the exposed pad connection point

  • 0 in reply to Undrea Fields
    Prodigy 90 points

    We believe that the ESD protection may be implemented only on the power-related lines, such as VCC, rather than on the RX & TX where the actual issues are occurring. 

    Based on our investigation, we've found that other parts of the IC-including VCC, I2C, other control lines-are not affected,, we think the damage appears to occur only on the pins directly connected to the image data lines, as shown the image I attached. 

  • 0 in reply to Kelley Kim
    TI__Genius 11940 points

    Hi Kelley,

    Do you have a local TI FAE or Marketing engineer you are working with?

    Regards,

    Undrea

  • 0 in reply to Undrea Fields
    Prodigy 90 points

    No,, we don't have.. 

  • 0 in reply to Undrea Fields
    Prodigy 90 points

    Would you please check it more? 

  • 0 in reply to Kelley Kim
    TI__Genius 11940 points

    Do you have full schematics/layout we can review?  I've sent a request previously to be able to send privately.

    Do you know if this failure always occurs on the EP or SoC side of the redriver?

    https://www.ti.com/support-quality/additional-information/customer-returns.html

    You can fill out the above form to start the process of investigating the failures for ESD damage.