DP83869HM: Phy detection inconsistency

Madhusankar SP

Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869

Tool/software:

HI Team,

I am currently working on a custom board based on the Xilinx Zynq UltraScale+ MPSoC and using the Texas Instruments DP83869HMRGZT Ethernet PHY. We are encountering a critical issue where the PHY is not consistently detected during the boot process.

In some instances, the PHY is correctly detected by U-Boot, while in others, it fails to initialize. This intermittent behavior is impacting the reliability of our system and is a major concern for our project.

Could you please assist us in identifying the root cause and suggest possible solutions or debugging steps to ensure consistent PHY detection?

below are my dts settings

&gem1 {
phy-mode = "rgmii";
status = "okay";
phy-handle = <&phy1>;
phy1: phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c22";
tx-fifo-depth = <0x01>;
rx-fifo-depth = <0x01>;
ti,op-mode = <0x00>;
rx-internal-delay-ps = <3000>;
tx-internal-delay-ps = <2000>;
interrupt-parent = <&gpio>;
interrupts = <78 8>;
};
};

Regards,
Madhusankar

2 months ago

0 Evan Mayhew 2 months ago

TI__Mastermind 24988 points

Hi Madhusankar,

What is the failure rate, and is the failure limited to driver binding / PHY detection over MDIO?

If there is no difference in DTS configuration between boots, these possible issues come to mind:

PHY is not powering properly, causing MDIO to not respond on boot.
PHY is powered, with some marginality on PHY address strap pin voltages causing different PHY address between boots.

To confirm (1), these peripheral pin checks can be done in pass/fail cases:

Voltage across RBIAS resistor ≈ 1V if PHY is alive
XI clock input is active and meeting 25M+/-100ppm requirement
RX_CLK is active output (frequency may vary)

To confirm (2), voltage on RX_D0 and RX_D1 pins can be measured on start-up for pass/fail cases.
Is RXD0 voltage ≈ 0.165 x VDDIO?
Is RXD1 voltage ≈ 0V?

Thank you,
Evan

0 Madhusankar SP 2 months ago in reply to Evan Mayhew

Prodigy 80 points

Hi Evan,

What is the failure rate, and is the failure limited to driver binding / PHY detection over MDIO?

Ans: 2 out of 10 detection fails in Uboot, All boot I can observe some activity over MDC/MDIO lines even if it is not detecting.

If there is no difference in DTS configuration between boots, these possible issues come to mind:

PHY is not powering properly, causing MDIO to not respond on boot.

Ans: Below given is the PHY power up sequence and its follows as per recommended in the datasheet for power up:

PHY is powered, with some marginality on PHY address strap pin voltages causing different PHY address between boots.

To confirm (1), these peripheral pin checks can be done in pass/fail cases:

Voltage across RBIAS resistor ≈ 1V if PHY is alive

Ans: Yes, voltage across RBIAS resistor is 1V.

XI clock input is active and meeting 25M+/-100ppm requirement

Ans: Yes, the clock input is 25MHz.

RX_CLK is active output (frequency may vary)

Ans: Yes, observed 2.5MHz clock all the time even when the PHY is not detecting.

To confirm (2), voltage on RX_D0 and RX_D1 pins can be measured on start-up for pass/fail cases.
Is RXD0 voltage ≈ 0.165 x V DDIO?

Ans: Voltage on RXD0 is 0.555V at reset

Is RXD1 voltage ≈ 0V?

Ans = Voltage at RXD1 is 0.34V at reset.

Please find the attached circuit in our board attached for your review, please let us know if any issue is there in the circuit we are following for ethernet PHY.

Also, even when the PHY is detecting, there is no link-up happening and when we connect the ethernet cable to the ethernet port, no LEDs are blinking/glowing. We are connecting the LED pins to Magjack connector as per MODE 0 of “Figure 7-16. Example Strap Connections” in datasheet.

DP83869HM-Circuit.pdf

Regards,

Madhusankar

0 Evan Mayhew 2 months ago in reply to Madhusankar SP

TI__Mastermind 24988 points

Hi Madhusankar,

RXD1 voltage is above the Vmax limit for Mode 0, which may cause PHY address to strap to unintended value on some power cycles. Is it possible to test with RXD1 strap voltage = 0V on start-up, and note failure rate to detect PHY?

Thank you,
Evan

0 Madhusankar SP 2 months ago in reply to Evan Mayhew

Prodigy 80 points

Hi Evan,

We have made the PHY address strap pins to PHY AD ?[0:3] = 0111, now the PHY detection is happening consistently.

But I have one more query regarding the strap pins of OPMODE.

In Revision C of DP83869 datasheet state that for two level strapping table, for mode 0 - Rhi should be open and Rlo should be connected to GND using 2.49Kohm.

But in revision D datasheet, in the same two level strap it is mentioned to keep both Rlo and Rhi as "Open".

But in the revision history of the Revision datasheet states "4-Level Strapping Mode 0 Rlo recommendation changed from 2.49k to OPEN", but the 4 level strap table doesn't have any changes.

Could you please explain what should be the correct Rhi and Rlo resistor values/condition for MODE0 and MODE1 of two level strapping?

Regards,

Madhusankar

0 Evan Mayhew 2 months ago in reply to Madhusankar SP

TI__Mastermind 24988 points

Hi Madhusankar,

Sorry for the confusion, the revision history notes are referring to 2-level strap table, not 4-level table. This revision was made as PD resistor is not typically required on strapping pins due to PHY's internal PD resistor. In your case with OPEN/OPEN resulting in 0.34V at reset, it seems there is some other component (or MAC) loading the pin during reset/power.

To avoid this, testing could be done with PHY powered first before MAC. If this power sequence is not possible, 2.49k PD on the pin is recommended to prevent load effect from changing PHY strap value.

Thank you,
Evan

0 Madhusankar SP 2 months ago in reply to Evan Mayhew

Prodigy 80 points

Hi Evan,

I have attached the updated schematic with strap changes done in the circuit. Kindly let us know if you have any feedback or suggestions regarding the schematic.

However, we are able to link up 100Mbps but not 1000Mbps in dynamic connection, but in static IP connection we are successfully able to linkup with 1000Mbps, could you please guide us what can be the reason for this?

DP83869-Circuit-updated.pdf

Regards,

Madhusankar

0 Evan Mayhew 2 months ago in reply to Madhusankar SP

TI__Mastermind 24988 points

Hi Madhusankar,

Schematic connections look good, I don't see any concerns that would cause this 1G link issue.

Could you please share the PHY register dump for below cases:

- Static IP config with 1G link-up
- Dynamic IP config with 1G link failure

If IP config method is the only difference between setups, my assumption is that some address resolution (DHCP...) packets on the line are interfering with auto-negotiation on start-up.

For quick test, do you see link-up in failing case when restarting auto-negotiation (0x0[9] = '1')?

Does forcing speed to 1G on both PHYs allow for link-up / communication?

Thank you,
Evan

0 Madhusankar SP 2 months ago in reply to Evan Mayhew

Prodigy 80 points

HI Evan,

Please find attached the register readouts obtained from both static and dynamic IP configuration attempts for your reference.We attempted to set the 9th bit of register 0x0 (BMCR) to '1' in order to enable auto-negotiation; however, the bit value did not change as expected. To further investigate, we then asserted a PHY reset by setting the 15th bit of BMCR. After the reset, we again attempted to set the 9th bit high, but the value still remained unchanged, and the link-up did not occur.
For clarity, we have attached a snapshot demonstrating the procedure we followed for writing to the registers.

Fullscreen reg_dump_dynamic.txt Download

root@zynqmp-iwg36m:~# 
root@zynqmp-iwg36m:~# ./reg_read.sh 
0x00 = 0x1140
0x01 = 0x7949
0x02 = 0x2000
0x03 = 0xA0F3
0x04 = 0x09E1
0x05 = 0x0000
0x06 = 0x0065
0x07 = 0x2001
0x08 = 0x0000
0x09 = 0x0B00
0x0A = 0x0000
0x0B = 0x0000
0x0C = 0x0000
0x0D = 0x4007
0x0E = 0x0000
0x0F = 0xF000
0x10 = 0x5048
0x11 = 0x0302
0x12 = 0xEC10
0x13 = 0x0040
0x14 = 0x2BC7
0x15 = 0x0000
0x16 = 0x0000
0x17 = 0x0040
0x18 = 0x6150
0x19 = 0x4444
0x1A = 0x0002
0x1B = 0x0000
0x1C = 0x0000
0x1D = 0x0000
0x1E = 0x0092
0x1F = 0x0000
0x0025 = 0x0480
0x002C = 0x141F
0x002D = 0x0000
0x002E = 0x0221
0x0031 = 0x10B0
0x0032 = 0x00D3
0x0033 = 0x0000
0x0037 = 0x0000
0x0039 = 0x0000
0x003A = 0x0000
0x0043 = 0x07A0
0x004F = 0x0200
0x0055 = 0x0000
0x006E = 0x0070
0x0071 = 0x0000
0x0072 = 0x0000
0x007B = 0x05DC
0x007C = 0x007D
0x0086 = 0x0077
0x00A0 = 0x0503
0x00A1 = 0x0804
0x00A2 = 0x1010
0x00A3 = 0x1010
0x00C6 = 0x0000
0x00D6 = 0x0000
0x00E9 = 0x9F22
0x00FE = 0xE721
0x0134 = 0x1000
0x0135 = 0x0000
0x0136 = 0x0000
0x0137 = 0x0000
0x0138 = 0x0000
0x0139 = 0x0000
0x013A = 0x0000
0x013B = 0x0000
0x013C = 0x0000
0x013D = 0x0000
0x013E = 0x0000
0x013F = 0x0000
0x0140 = 0x0000
0x0141 = 0x0000
0x0142 = 0x0000
0x0143 = 0x0000
0x0144 = 0x0000
0x0145 = 0x0000
0x0146 = 0x0000
0x0147 = 0x0000
0x0148 = 0x0000
0x0149 = 0x0000
0x014A = 0x0000
0x014B = 0x0000
0x014C = 0x0000
0x014D = 0x0000
0x014E = 0x0000
0x014F = 0x0000
0x0150 = 0x0000
0x0151 = 0x0000
0x0152 = 0x0000
0x0153 = 0x0000
0x0154 = 0x0000
0x0155 = 0x0000
0x0156 = 0x0000
0x0157 = 0x0000
0x0158 = 0x0000
0x0159 = 0x0000
0x015A = 0x0000
0x015B = 0x0000
0x015C = 0x0000
0x015D = 0x0000
0x015E = 0x0000
0x015F = 0x0000
0x016F = 0x0095
0x0170 = 0x0C0E
0x0180 = 0x0752
0x0181 = 0xC850
0x0182 = 0x5326
0x0183 = 0xA01E
0x0184 = 0xE976
0x0185 = 0x19CF
0x0190 = 0x0000
0x0191 = 0x0000
0x0192 = 0x0000
0x0193 = 0x0000
0x0194 = 0x0000
0x0195 = 0x0000
0x0196 = 0x0000
0x0197 = 0x0000
0x0198 = 0x0000
0x0199 = 0x0000
0x01A4 = 0x0000
0x01A5 = 0x0000
0x01A6 = 0x0000
0x01A8 = 0x0000
0x01A9 = 0x0000
0x01DF = 0x0000
0x01E0 = 0x417A
0x01EC = 0x1FFD
0x0C00 = 0x0140
0x0C01 = 0x6149
0x0C02 = 0x2000
0x0C03 = 0xA0F3
0x0C04 = 0x0020
0x0C05 = 0x0000
0x0C06 = 0x0000
0x0C07 = 0x2001
0x0C08 = 0x0000
0x0C10 = 0x3348
0x0C18 = 0x01FF
0x0C19 = 0x0000
0x0C1A = 0x0000
0x0C30 = 0x3056

Fullscreen reg_dump_static.txt Download

root@zynqmp-iwg36m:~# 
root@zynqmp-iwg36m:~# ./reg_read.sh 
0x00 = 0x1140
0x01 = 0x796D
0x02 = 0x2000
0x03 = 0xA0F3
0x04 = 0x09E1
0x05 = 0xCDE1
0x06 = 0x006D
0x07 = 0x2001
0x08 = 0x4006
0x09 = 0x0B00
0x0A = 0x787A
0x0B = 0x0000
0x0C = 0x0000
0x0D = 0x401F
0x0E = 0x3056
0x0F = 0xF000
0x10 = 0x5048
0x11 = 0xAC02
0x12 = 0xEC10
0x13 = 0x0104
0x14 = 0x2BC7
0x15 = 0x0002
0x16 = 0x0000
0x17 = 0x0040
0x18 = 0x6150
0x19 = 0x4444
0x1A = 0x0002
0x1B = 0x0000
0x1C = 0x0000
0x1D = 0x0000
0x1E = 0x0092
0x1F = 0x0000
0x0025 = 0x0480
0x002C = 0x141F
0x002D = 0x0000
0x002E = 0x0221
0x0031 = 0x10B0
0x0032 = 0x40D3
0x0033 = 0x0000
0x0037 = 0x0000
0x0039 = 0x0000
0x003A = 0x0000
0x0043 = 0x07A0
0x004F = 0x0200
0x0055 = 0x0000
0x006E = 0x0070
0x0071 = 0x0000
0x0072 = 0x0000
0x007B = 0x05DC
0x007C = 0x007D
0x0086 = 0x0077
0x00A0 = 0x0503
0x00A1 = 0x0804
0x00A2 = 0x1010
0x00A3 = 0x1010
0x00C6 = 0x0000
0x00D6 = 0x0000
0x00E9 = 0x9F22
0x00FE = 0xE721
0x0134 = 0x1000
0x0135 = 0x0000
0x0136 = 0x0000
0x0137 = 0x0000
0x0138 = 0x0000
0x0139 = 0x0000
0x013A = 0x0000
0x013B = 0x0000
0x013C = 0x0000
0x013D = 0x0000
0x013E = 0x0000
0x013F = 0x0000
0x0140 = 0x0000
0x0141 = 0x0000
0x0142 = 0x0000
0x0143 = 0x0000
0x0144 = 0x0000
0x0145 = 0x0000
0x0146 = 0x0000
0x0147 = 0x0000
0x0148 = 0x0000
0x0149 = 0x0000
0x014A = 0x0000
0x014B = 0x0000
0x014C = 0x0000
0x014D = 0x0000
0x014E = 0x0000
0x014F = 0x0000
0x0150 = 0x0000
0x0151 = 0x0000
0x0152 = 0x0000
0x0153 = 0x0000
0x0154 = 0x0000
0x0155 = 0x0000
0x0156 = 0x0000
0x0157 = 0x0000
0x0158 = 0x0000
0x0159 = 0x0000
0x015A = 0x0000
0x015B = 0x0000
0x015C = 0x0000
0x015D = 0x0000
0x015E = 0x0000
0x015F = 0x0000
0x016F = 0x0095
0x0170 = 0x0C0E
0x0180 = 0x0752
0x0181 = 0xC850
0x0182 = 0x5326
0x0183 = 0xA01E
0x0184 = 0xE976
0x0185 = 0x19CF
0x0190 = 0x0000
0x0191 = 0x0000
0x0192 = 0x0000
0x0193 = 0x0000
0x0194 = 0x0000
0x0195 = 0x0000
0x0196 = 0x0000
0x0197 = 0x0000
0x0198 = 0x0000
0x0199 = 0x0000
0x01A4 = 0x0000
0x01A5 = 0x0000
0x01A6 = 0x0000
0x01A8 = 0x0000
0x01A9 = 0x0000
0x01DF = 0x0000
0x01E0 = 0x417A
0x01EC = 0x1FFD
0x0C00 = 0x0140
0x0C01 = 0x6149
0x0C02 = 0x2000
0x0C03 = 0xA0F3
0x0C04 = 0x0020
0x0C05 = 0x0000
0x0C06 = 0x0000
0x0C07 = 0x2001
0x0C08 = 0x0000
0x0C10 = 0x3348
0x0C18 = 0x01FF
0x0C19 = 0x0000
0x0C1A = 0x0000
0x0C30 = 0x3056

Regards,
Madhusankar SP

0 Evan Mayhew 2 months ago in reply to Madhusankar SP

TI__Mastermind 24988 points

Hi Madhusankar,

Interesting... dynamic IP configuration causes auto-negotiation failure from this result.

Which device is being used as the link partner? Generally I don't expect IP configuration to affect auto-negotiation process, but it's possible the link partner SoC has some dependency on IP resolution before allowing the PHY to communicate.

Do you have test points for the MDI line? It would help to see if Fast Link Pulses are observed on the line during start-up in each case.

Thank you,
Evan

0 Madhusankar SP 2 months ago in reply to Evan Mayhew

Prodigy 80 points

HI Evan,

We had some issue in H/W, it was because of grounding of Magjack connector was not proper. Now after correcting that issue, 1G linkup is happening.But auto-negotiation off is not happening.Means after turning off the auto-negotiation and am setting the speed to 100mbps , link-up is not happening.If I use a 100Mbps hub/switch then made auto-negotiation off am able to change the speed.

Regards,
Madhusankar SP

0 Evan Mayhew 2 months ago in reply to Madhusankar SP

TI__Mastermind 24988 points

Hi Madhusankar,

Glad to see auto-negotiation is working.

Disabling auto-negotiation on the PHY requires the link partner to also disable auto-neg and force the same speed. Could you please confirm the link partner you are using, and the configuration set for forced speed?

Thank you,
Evan

0 Madhusankar SP 2 months ago in reply to Evan Mayhew

Prodigy 80 points

Hi Evan,

Thanks for your support.We have two additional Ethernet PHYs that share a common MDC/MDIO bus, but each PHY has a separate reset GPIO line. We are evaluating the reset requirements for PHYs in this shared MDC/MDIO configuration.

During testing, both of the PHYs are successfully detected when configured with a dedicated MDC/MDIO interface. However, when both PHYs were connected to the shared MDC/MDIO bus, neither PHY was detected.

Could you please clarify the recommended reset sequencing or constraints when using multiple PHYs with shared MDC/MDIO but individual reset controls.

Regards,
Madhusankar SP

0 Madhusankar SP 2 months ago in reply to Madhusankar SP

Prodigy 80 points

Hi Evan,

The both phys which has shared MDC/MDIO we are using in SGMII mode.

Regards,
Madhusankar SP

0 Evan Mayhew 2 months ago in reply to Madhusankar SP

TI__Mastermind 24988 points

Hi Madhusankar,

The main constraint is PHY address strapping - each PHY must have a unique PHY address strapped via RX_D0 and RX_D1 pins to allow MAC to distinguish between them on a shared bus.

The DTS entry for each PHY needs to match each unique PHY address.

Thank you,
Evan

0 Madhusankar SP 2 months ago in reply to Evan Mayhew

Prodigy 80 points

Hi Evan,

We are using unique PHY address for each PHY.Please find the below dts settings and PHY address.Here GEM1 has dedicated MDC/MDIO.

PHY 1 = 0001

PHY 2 = 0011

PHY3 = 1111

&gem1 {
phy-mode = "rgmii-id";
status = "okay";
phy-handle = <&phy1>;
phy1: phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c22";
rx-internal-delay-ps = <2000>;
tx-internal-delay-ps = <2000>;
};
};

&gem2 {
phy-mode = "sgmii";
status = "okay";
phy-handle = <&phyf>;
phy-reset-gpio = <&gpio 81 1>;
phyf: phy@f {
reg = <0xf>;
compatible = "ethernet-phy-ieee802.3-c22";
rx-internal-delay-ps = <2000>;
tx-internal-delay-ps = <2000>;
};
phy3: phy@3 {
reg = <0x3>;
compatible = "ethernet-phy-ieee802.3-c22";
rx-internal-delay-ps = <2000>;
tx-internal-delay-ps = <2000>;
};

};

&gem3 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy3>;
};

Regards,
Madhusankar SP

0 Evan Mayhew 2 months ago in reply to Madhusankar SP

TI__Mastermind 24988 points

Hi Madhusankar,

Are all three PHYs powered or reset at same time during boot? Please confirm if recommended reset sequence is being followed:

Is the issue only with PHY detection during boot? Are you able to access the PHY registers with phytool or another utility separately? I would like to confirm if this is H/W issue with PHY health, or some timing requirement with SoC state machine to properly detect PHYs.

Thank you,
Evan

0 Madhusankar SP 2 months ago in reply to Evan Mayhew

Prodigy 80 points

HI Evan,

Thank you very much for your support now all the PHYs are working fine with polling mode.But when configuring interrupt mode getting below crash prints.Als please find the device tree settings, for all the PHY same crash is observing.

[2025-07-15 10:37:54] [   21.798104] audit: type=1327 audit(1709054777.744:2): proctitle="(systemd)"
[2025-07-15 10:37:55] [   22.885989] irq 56: nobody cared (try booting with the "irqpoll" option)
[2025-07-15 10:37:56] [   22.892701] CPU: 0 PID: 741 Comm: systemd Not tainted 6.6.40-xilinx-g0b36ba42be64 #1
[2025-07-15 10:37:56] [   22.900447] Hardware name: xlnx,zynqmp (DT)
[2025-07-15 10:37:56] [   22.904623] Call trace:
[2025-07-15 10:37:56] [   22.907061] dump_backtrace+0x90/0xe8
[2025-07-15 10:37:56] [   22.910732] show_stack+0x18/0x24
[2025-07-15 10:37:56] [   22.914048] dump_stack_lvl+0x48/0x60
[2025-07-15 10:37:56] [   22.917711] dump_stack+0x18/0x24
[2025-07-15 10:37:56] [   22.921027] __report_bad_irq+0x38/0x120
[2025-07-15 10:37:56] [   22.924950] note_interrupt+0x310/0x360
[2025-07-15 10:37:56] [   22.928786] handle_irq_event+0xd8/0xe8
[2025-07-15 10:37:56] [   22.932623] handle_fasteoi_irq+0xb0/0x284
[2025-07-15 10:37:56] [   22.936720] generic_handle_domain_irq+0x2c/0x44
[2025-07-15 10:37:56] [   22.941347] zynq_gpio_irqhandler+0xa0/0x16c
[2025-07-15 10:37:56] [   22.945617] generic_handle_domain_irq+0x2c/0x44
[2025-07-15 10:37:56] [   22.950244] gic_handle_irq+0x6c/0x9c
[2025-07-15 10:37:56] [   22.953907] call_on_irq_stack+0x24/0x4c
[2025-07-15 10:37:56] [   22.957830] do_interrupt_handler+0x80/0x84
[2025-07-15 10:37:56] [   22.962014] el0_interrupt+0x50/0xd8
[2025-07-15 10:37:56] [   22.965590] __el0_irq_handler_common+0x18/0x24
[2025-07-15 10:37:56] [   22.970121] el0t_64_irq_handler+0x10/0x1c
[2025-07-15 10:37:56] [   22.974218] el0t_64_irq+0x190/0x194
[2025-07-15 10:37:56] [   22.977794] handlers:
[2025-07-15 10:37:56] [   22.980060] [<0000000076a29780>] irq_default_primary_handler threaded [<00000000a58e1e22>] phy_interrupt
[2025-07-15 10:37:56] [   22.989564] Disabling IRQ #56

device tree
================
&gem2 {
phy-mode = "sgmii";
status = "okay";
phy-handle = <&phyf>;
phy-reset-gpio = <&gpio 81 1>;
};

&gem3 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy3>;
phy3: phy@3 {
reg = <0x3>;
compatible = "ethernet-phy-ieee802.3-c22";
ti,op-mode = <0x06>;
rx-internal-delay-ps = <2000>;
tx-internal-delay-ps = <2000>;
interrupt-parent = <&gpio>;
interrupts = <79 8>;
};
phyf: phy@f {
reg = <0xf>;
compatible = "ethernet-phy-ieee802.3-c22";
ti,op-mode = <0x06>;
rx-internal-delay-ps = <2000>;
tx-internal-delay-ps = <2000>;
interrupt-parent = <&gpio>;
interrupts = <28 8>;
};

};

&gem1 {
phy-mode = "rgmii-id";
status = "okay";
phy-handle = <&phy1>;
phy1: phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c22";
rx-internal-delay-ps = <2000>;
tx-internal-delay-ps = <2000>;
interrupt-parent = <&gpio>;
interrupts = <78 8>;
};
};

Regards
Madhusankar SP

0 Evan Mayhew 2 months ago in reply to Madhusankar SP

TI__Mastermind 24988 points

Hi Madhusankar,

Please try booting with irqpoll option enabled. Does the system boot fail, or it only disables IRQ and is still able to function for link/communication?

Thank you,
Evan

0 Madhusankar SP 1 month ago in reply to Evan Mayhew

Prodigy 80 points

Hi Evan,

I have tried booting with irqpoll option enabled, the system boots completely without the crash prints.But link communication is not happening.

Regards,
Madhusankar SP

0 Evan Mayhew 1 month ago in reply to Madhusankar SP

TI__Mastermind 24988 points

Hi Madhusankar,

As there is a prior case with your system booting and function for link in polling mode, could you please share a register dump between passing/failing cases for comparison? This will help isolate any PHY configuration difference between each case.

I don't have exposure to failing conditions for interrupt mode - is it possible to see if the required interrupt condition is being received from the driver?

Thank you,
Evan

0 Madhusankar SP 1 month ago in reply to Evan Mayhew

Prodigy 80 points

Hi Evan,

Just to clarify—our passing case occurs when the following properties are omitted from the device tree:

interrupt-parent = <&gpio>;

interrupts = <78 8>;

Could you please confirm if this aligns with what you referred to as polling mode, or were you suggesting booting with the irqpoll kernel parameter?

Additionally, in which of these scenarios would you recommend dumping the registers for further analysis?

Regards
Madhusankar

0 Evan Mayhew 1 month ago in reply to Madhusankar SP

TI__Mastermind 24988 points

Hi Madhusankar,

I am referring to:

1) Passing case with interrupt properties omitted from device tree
2) Failing case with irqpoll parameter enabled

Sharing register dumps in each of these cases will help isolate possible register configuration issues to debug failing case in (2).

Thank you,
Evan

0 Madhusankar SP 1 month ago in reply to Evan Mayhew

Prodigy 80 points

HI EVAN.

Please find the register dump of both fail case and pass case.

Fullscreen pass_case.txt Download

[2025-08-04 10:53:27] root@zynqmp-iwg36o:~# 
[2025-08-04 10:53:27] root@zynqmp-iwg36o:~# ./reg_read.sh 
[2025-08-04 10:53:34] C22 0x00 = 0x1140
[2025-08-04 10:53:34] C22 0x01 = 0x796D
[2025-08-04 10:53:34] C22 0x02 = 0x2000
[2025-08-04 10:53:34] C22 0x03 = 0xA0F3
[2025-08-04 10:53:34] C22 0x04 = 0x09E1
[2025-08-04 10:53:35] C22 0x05 = 0xC5E1
[2025-08-04 10:53:35] C22 0x06 = 0x006F
[2025-08-04 10:53:35] C22 0x07 = 0x2001
[2025-08-04 10:53:35] C22 0x08 = 0x4806
[2025-08-04 10:53:35] C22 0x09 = 0x0B00
[2025-08-04 10:53:35] C22 0x0A = 0x3800
[2025-08-04 10:53:35] C22 0x0B = 0x0000
[2025-08-04 10:53:35] C22 0x0C = 0x0000
[2025-08-04 10:53:35] C22 0x0D = 0x4007
[2025-08-04 10:53:35] C22 0x0E = 0x0000
[2025-08-04 10:53:35] C22 0x0F = 0xF000
[2025-08-04 10:53:35] C22 0x10 = 0x5048
[2025-08-04 10:53:35] C22 0x11 = 0xBC02
[2025-08-04 10:53:35] C22 0x12 = 0x0000
[2025-08-04 10:53:35] C22 0x13 = 0x1C40
[2025-08-04 10:53:35] C22 0x14 = 0x2BC7
[2025-08-04 10:53:35] C22 0x15 = 0x0000
[2025-08-04 10:53:35] C22 0x16 = 0x0000
[2025-08-04 10:53:35] C22 0x17 = 0x0040
[2025-08-04 10:53:35] C22 0x18 = 0x6150
[2025-08-04 10:53:35] C22 0x19 = 0x4444
[2025-08-04 10:53:35] C22 0x1A = 0x0002
[2025-08-04 10:53:35] C22 0x1B = 0x0000
[2025-08-04 10:53:35] C22 0x1C = 0x0000
[2025-08-04 10:53:35] C22 0x1D = 0x0000
[2025-08-04 10:53:35] C22 0x1E = 0x0012
[2025-08-04 10:53:35] C22 0x1F = 0x0000
[2025-08-04 10:53:35] C45 0x0025 = 0x0480
[2025-08-04 10:53:35] C45 0x002C = 0x141F
[2025-08-04 10:53:35] C45 0x002D = 0x0000
[2025-08-04 10:53:35] C45 0x002E = 0x0221
[2025-08-04 10:53:35] C45 0x0031 = 0x10B0
[2025-08-04 10:53:35] C45 0x0032 = 0x00D0
[2025-08-04 10:53:35] C45 0x0033 = 0x0000
[2025-08-04 10:53:35] C45 0x0037 = 0x0000
[2025-08-04 10:53:35] C45 0x0039 = 0x0000
[2025-08-04 10:53:35] C45 0x003A = 0x0000
[2025-08-04 10:53:35] C45 0x0043 = 0x07A0
[2025-08-04 10:53:35] C45 0x004F = 0x0200
[2025-08-04 10:53:35] C45 0x0055 = 0x0000
[2025-08-04 10:53:35] C45 0x006E = 0x0010
[2025-08-04 10:53:35] C45 0x0071 = 0x0000
[2025-08-04 10:53:35] C45 0x0072 = 0x0000
[2025-08-04 10:53:35] C45 0x007B = 0x05DC
[2025-08-04 10:53:35] C45 0x007C = 0x007D
[2025-08-04 10:53:35] C45 0x0086 = 0x0077
[2025-08-04 10:53:35] C45 0x00A0 = 0x0503
[2025-08-04 10:53:35] C45 0x00A1 = 0x0804
[2025-08-04 10:53:35] C45 0x00A2 = 0x1010
[2025-08-04 10:53:35] C45 0x00A3 = 0x1010
[2025-08-04 10:53:35] C45 0x00C6 = 0x0000
[2025-08-04 10:53:35] C45 0x00D6 = 0x0000
[2025-08-04 10:53:35] C45 0x00E9 = 0x9F22
[2025-08-04 10:53:35] C45 0x00FE = 0xE721
[2025-08-04 10:53:35] C45 0x0134 = 0x1000
[2025-08-04 10:53:35] C45 0x0135 = 0x0000
[2025-08-04 10:53:35] C45 0x0136 = 0x0000
[2025-08-04 10:53:35] C45 0x0137 = 0x0000
[2025-08-04 10:53:35] C45 0x0138 = 0x0000
[2025-08-04 10:53:35] C45 0x0139 = 0x0000
[2025-08-04 10:53:35] C45 0x013A = 0x0000
[2025-08-04 10:53:35] C45 0x013B = 0x0000
[2025-08-04 10:53:35] C45 0x013C = 0x0000
[2025-08-04 10:53:35] C45 0x013D = 0x0000
[2025-08-04 10:53:35] C45 0x013E = 0x0000
[2025-08-04 10:53:35] C45 0x013F = 0x0000
[2025-08-04 10:53:35] C45 0x0140 = 0x0000
[2025-08-04 10:53:35] C45 0x0141 = 0x0000
[2025-08-04 10:53:35] C45 0x0142 = 0x0000
[2025-08-04 10:53:35] C45 0x0143 = 0x0000
[2025-08-04 10:53:35] C45 0x0144 = 0x0000
[2025-08-04 10:53:35] C45 0x0145 = 0x0000
[2025-08-04 10:53:35] C45 0x0146 = 0x0000
[2025-08-04 10:53:35] C45 0x0147 = 0x0000
[2025-08-04 10:53:35] C45 0x0148 = 0x0000
[2025-08-04 10:53:35] C45 0x0149 = 0x0000
[2025-08-04 10:53:35] C45 0x014A = 0x0000
[2025-08-04 10:53:35] C45 0x014B = 0x0000
[2025-08-04 10:53:35] C45 0x014C = 0x0000
[2025-08-04 10:53:35] C45 0x014D = 0x0000
[2025-08-04 10:53:35] C45 0x014E = 0x0000
[2025-08-04 10:53:35] C45 0x014F = 0x0000
[2025-08-04 10:53:35] C45 0x0150 = 0x0000
[2025-08-04 10:53:36] C45 0x0151 = 0x0000
[2025-08-04 10:53:36] C45 0x0152 = 0x0000
[2025-08-04 10:53:36] C45 0x0153 = 0x0000
[2025-08-04 10:53:36] C45 0x0154 = 0x0000
[2025-08-04 10:53:36] C45 0x0155 = 0x0000
[2025-08-04 10:53:36] C45 0x0156 = 0x0000
[2025-08-04 10:53:36] C45 0x0157 = 0x0000
[2025-08-04 10:53:36] C45 0x0158 = 0x0000
[2025-08-04 10:53:36] C45 0x0159 = 0x0000
[2025-08-04 10:53:36] C45 0x015A = 0x0000
[2025-08-04 10:53:36] C45 0x015B = 0x0000
[2025-08-04 10:53:36] C45 0x015C = 0x0000
[2025-08-04 10:53:36] C45 0x015D = 0x0000
[2025-08-04 10:53:36] C45 0x015E = 0x0000
[2025-08-04 10:53:36] C45 0x015F = 0x0000
[2025-08-04 10:53:36] C45 0x016F = 0x0095
[2025-08-04 10:53:36] C45 0x0170 = 0x0C0E
[2025-08-04 10:53:36] C45 0x0180 = 0x0752
[2025-08-04 10:53:36] C45 0x0181 = 0xC850
[2025-08-04 10:53:36] C45 0x0182 = 0x5326
[2025-08-04 10:53:36] C45 0x0183 = 0xA01E
[2025-08-04 10:53:36] C45 0x0184 = 0xE976
[2025-08-04 10:53:36] C45 0x0185 = 0x19CF
[2025-08-04 10:53:36] C45 0x0190 = 0x0000
[2025-08-04 10:53:36] C45 0x0191 = 0x0000
[2025-08-04 10:53:36] C45 0x0192 = 0x0000
[2025-08-04 10:53:36] C45 0x0193 = 0x0000
[2025-08-04 10:53:36] C45 0x0194 = 0x0000
[2025-08-04 10:53:36] C45 0x0195 = 0x0000
[2025-08-04 10:53:36] C45 0x0196 = 0x0000
[2025-08-04 10:53:36] C45 0x0197 = 0x0000
[2025-08-04 10:53:36] C45 0x0198 = 0x0000
[2025-08-04 10:53:36] C45 0x0199 = 0x0000
[2025-08-04 10:53:36] C45 0x01A4 = 0x0000
[2025-08-04 10:53:36] C45 0x01A5 = 0x0000
[2025-08-04 10:53:36] C45 0x01A6 = 0x0000
[2025-08-04 10:53:36] C45 0x01A8 = 0x0000
[2025-08-04 10:53:36] C45 0x01A9 = 0x0000
[2025-08-04 10:53:36] C45 0x01DF = 0x0000
[2025-08-04 10:53:36] C45 0x01E0 = 0x417A
[2025-08-04 10:53:36] C45 0x01EC = 0x1FFD
[2025-08-04 10:53:36] C45 0x0C00 = 0x0140
[2025-08-04 10:53:36] C45 0x0C01 = 0x6149
[2025-08-04 10:53:36] C45 0x0C02 = 0x2000
[2025-08-04 10:53:36] C45 0x0C03 = 0xA0F3
[2025-08-04 10:53:36] C45 0x0C04 = 0x0020
[2025-08-04 10:53:36] C45 0x0C05 = 0x0000
[2025-08-04 10:53:36] C45 0x0C06 = 0x0000
[2025-08-04 10:53:36] C45 0x0C07 = 0x2001
[2025-08-04 10:53:36] C45 0x0C08 = 0x0000
[2025-08-04 10:53:36] C45 0x0C10 = 0x3348
[2025-08-04 10:53:36] C45 0x0C18 = 0x01FF
[2025-08-04 10:53:36] C45 0x0C19 = 0x0010
[2025-08-04 10:53:36] C45 0x0C1A = 0x0000
[2025-08-04 10:53:36] C45 0x0C30 = 0x3056
[2025-08-04 10:53:36] root@zynqmp-iwg36o:~#

Fullscreen FAIL_CASE.txt Download

[2025-08-04 11:48:48] root@zynqmp-iwg36o:~# 
[2025-08-04 11:48:48] root@zynqmp-iwg36o:~# ./reg_read.sh 
[2025-08-04 11:48:51] C22 0x00 = 0x1140
[2025-08-04 11:48:51] C22 0x01 = 0x796D
[2025-08-04 11:48:51] C22 0x02 = 0x2000
[2025-08-04 11:48:51] C22 0x03 = 0xA0F3
[2025-08-04 11:48:51] C22 0x04 = 0x09E1
[2025-08-04 11:48:51] C22 0x05 = 0xC5E1
[2025-08-04 11:48:51] C22 0x06 = 0x006F
[2025-08-04 11:48:51] C22 0x07 = 0x2001
[2025-08-04 11:48:51] C22 0x08 = 0x4806
[2025-08-04 11:48:51] C22 0x09 = 0x0B00
[2025-08-04 11:48:51] C22 0x0A = 0x3800
[2025-08-04 11:48:51] C22 0x0B = 0x0000
[2025-08-04 11:48:51] C22 0x0C = 0x0000
[2025-08-04 11:48:51] C22 0x0D = 0x4007
[2025-08-04 11:48:51] C22 0x0E = 0x0000
[2025-08-04 11:48:51] C22 0x0F = 0xF000
[2025-08-04 11:48:51] C22 0x10 = 0x5048
[2025-08-04 11:48:51] C22 0x11 = 0xBF02
[2025-08-04 11:48:51] C22 0x12 = 0xEC10
[2025-08-04 11:48:51] C22 0x13 = 0x0000
[2025-08-04 11:48:51] C22 0x14 = 0x2BC7
[2025-08-04 11:48:51] C22 0x15 = 0x0000
[2025-08-04 11:48:51] C22 0x16 = 0x0000
[2025-08-04 11:48:51] C22 0x17 = 0x0040
[2025-08-04 11:48:51] C22 0x18 = 0x6150
[2025-08-04 11:48:51] C22 0x19 = 0x4444
[2025-08-04 11:48:51] C22 0x1A = 0x0002
[2025-08-04 11:48:51] C22 0x1B = 0x0000
[2025-08-04 11:48:51] C22 0x1C = 0x0000
[2025-08-04 11:48:51] C22 0x1D = 0x0000
[2025-08-04 11:48:51] C22 0x1E = 0x0092
[2025-08-04 11:48:51] C22 0x1F = 0x0000
[2025-08-04 11:48:51] C45 0x0025 = 0x0480
[2025-08-04 11:48:51] C45 0x002C = 0x141F
[2025-08-04 11:48:51] C45 0x002D = 0x0000
[2025-08-04 11:48:51] C45 0x002E = 0x0221
[2025-08-04 11:48:51] C45 0x0031 = 0x10B0
[2025-08-04 11:48:51] C45 0x0032 = 0x00D0
[2025-08-04 11:48:51] C45 0x0033 = 0x0000
[2025-08-04 11:48:51] C45 0x0037 = 0x0000
[2025-08-04 11:48:51] C45 0x0039 = 0x0000
[2025-08-04 11:48:51] C45 0x003A = 0x0000
[2025-08-04 11:48:51] C45 0x0043 = 0x07A0
[2025-08-04 11:48:51] C45 0x004F = 0x0200
[2025-08-04 11:48:51] C45 0x0055 = 0x0001
[2025-08-04 11:48:51] C45 0x006E = 0x0010
[2025-08-04 11:48:51] C45 0x0071 = 0x0000
[2025-08-04 11:48:51] C45 0x0072 = 0x0000
[2025-08-04 11:48:51] C45 0x007B = 0x05DC
[2025-08-04 11:48:52] C45 0x007C = 0x007D
[2025-08-04 11:48:52] C45 0x0086 = 0x0077
[2025-08-04 11:48:52] C45 0x00A0 = 0x0503
[2025-08-04 11:48:52] C45 0x00A1 = 0x0804
[2025-08-04 11:48:52] C45 0x00A2 = 0x1010
[2025-08-04 11:48:52] C45 0x00A3 = 0x1010
[2025-08-04 11:48:52] C45 0x00C6 = 0x0000
[2025-08-04 11:48:52] C45 0x00D6 = 0x0000
[2025-08-04 11:48:52] C45 0x00E9 = 0x9F22
[2025-08-04 11:48:52] C45 0x00FE = 0xE721
[2025-08-04 11:48:52] C45 0x0134 = 0x1000
[2025-08-04 11:48:52] C45 0x0135 = 0x0000
[2025-08-04 11:48:52] C45 0x0136 = 0x0000
[2025-08-04 11:48:52] C45 0x0137 = 0x0000
[2025-08-04 11:48:52] C45 0x0138 = 0x0000
[2025-08-04 11:48:52] C45 0x0139 = 0x0000
[2025-08-04 11:48:52] C45 0x013A = 0x0000
[2025-08-04 11:48:52] C45 0x013B = 0x0000
[2025-08-04 11:48:52] C45 0x013C = 0x0000
[2025-08-04 11:48:52] C45 0x013D = 0x0000
[2025-08-04 11:48:52] C45 0x013E = 0x0000
[2025-08-04 11:48:52] C45 0x013F = 0x0000
[2025-08-04 11:48:52] C45 0x0140 = 0x0000
[2025-08-04 11:48:52] C45 0x0141 = 0x0000
[2025-08-04 11:48:52] C45 0x0142 = 0x0000
[2025-08-04 11:48:52] C45 0x0143 = 0x0000
[2025-08-04 11:48:52] C45 0x0144 = 0x0000
[2025-08-04 11:48:52] C45 0x0145 = 0x0000
[2025-08-04 11:48:52] C45 0x0146 = 0x0000
[2025-08-04 11:48:52] C45 0x0147 = 0x0000
[2025-08-04 11:48:52] C45 0x0148 = 0x0000
[2025-08-04 11:48:52] C45 0x0149 = 0x0000
[2025-08-04 11:48:53] C45 0x014A = 0x0000
[2025-08-04 11:48:53] C45 0x014B = 0x0000
[2025-08-04 11:48:53] C45 0x014C = 0x0000
[2025-08-04 11:48:53] C45 0x014D = 0x0000
[2025-08-04 11:48:53] C45 0x014E = 0x0000
[2025-08-04 11:48:53] C45 0x014F = 0x0000
[2025-08-04 11:48:53] C45 0x0150 = 0x0000
[2025-08-04 11:48:53] C45 0x0151 = 0x0000
[2025-08-04 11:48:53] C45 0x0152 = 0x0000
[2025-08-04 11:48:53] C45 0x0153 = 0x0000
[2025-08-04 11:48:53] C45 0x0154 = 0x0000
[2025-08-04 11:48:53] C45 0x0155 = 0x0000
[2025-08-04 11:48:53] C45 0x0156 = 0x0000
[2025-08-04 11:48:53] C45 0x0157 = 0x0000
[2025-08-04 11:48:53] C45 0x0158 = 0x0000
[2025-08-04 11:48:53] C45 0x0159 = 0x0000
[2025-08-04 11:48:53] C45 0x015A = 0x0000
[2025-08-04 11:48:53] C45 0x015B = 0x0000
[2025-08-04 11:48:53] C45 0x015C = 0x0000
[2025-08-04 11:48:53] C45 0x015D = 0x0000
[2025-08-04 11:48:53] C45 0x015E = 0x0000
[2025-08-04 11:48:53] C45 0x015F = 0x0000
[2025-08-04 11:48:53] C45 0x016F = 0x0095
[2025-08-04 11:48:53] C45 0x0170 = 0x0C0E
[2025-08-04 11:48:53] C45 0x0180 = 0x0752
[2025-08-04 11:48:53] C45 0x0181 = 0xC850
[2025-08-04 11:48:53] C45 0x0182 = 0x5326
[2025-08-04 11:48:53] C45 0x0183 = 0xA01E
[2025-08-04 11:48:53] C45 0x0184 = 0xE976
[2025-08-04 11:48:54] C45 0x0185 = 0x19CF
[2025-08-04 11:48:54] C45 0x0190 = 0x0000
[2025-08-04 11:48:54] C45 0x0191 = 0x0000
[2025-08-04 11:48:54] C45 0x0192 = 0x0000
[2025-08-04 11:48:54] C45 0x0193 = 0x0000
[2025-08-04 11:48:54] C45 0x0194 = 0x0000
[2025-08-04 11:48:54] C45 0x0195 = 0x0000
[2025-08-04 11:48:54] C45 0x0196 = 0x0000
[2025-08-04 11:48:54] C45 0x0197 = 0x0000
[2025-08-04 11:48:54] C45 0x0198 = 0x0000
[2025-08-04 11:48:54] C45 0x0199 = 0x0000
[2025-08-04 11:48:54] C45 0x01A4 = 0x0000
[2025-08-04 11:48:54] C45 0x01A5 = 0x0000
[2025-08-04 11:48:54] C45 0x01A6 = 0x0000
[2025-08-04 11:48:54] C45 0x01A8 = 0x0000
[2025-08-04 11:48:54] C45 0x01A9 = 0x0000
[2025-08-04 11:48:54] C45 0x01DF = 0x0000
[2025-08-04 11:48:54] C45 0x01E0 = 0x417A
[2025-08-04 11:48:54] C45 0x01EC = 0x1FFD
[2025-08-04 11:48:54] C45 0x0C00 = 0x0140
[2025-08-04 11:48:54] C45 0x0C01 = 0x6149
[2025-08-04 11:48:54] C45 0x0C02 = 0x2000
[2025-08-04 11:48:54] C45 0x0C03 = 0xA0F3
[2025-08-04 11:48:54] C45 0x0C04 = 0x0020
[2025-08-04 11:48:54] C45 0x0C05 = 0x0000
[2025-08-04 11:48:54] C45 0x0C06 = 0x0000
[2025-08-04 11:48:54] C45 0x0C07 = 0x2001
[2025-08-04 11:48:54] C45 0x0C08 = 0x0000
[2025-08-04 11:48:54] C45 0x0C10 = 0x3348
[2025-08-04 11:48:55] C45 0x0C18 = 0x01FF
[2025-08-04 11:48:55] C45 0x0C19 = 0x0010
[2025-08-04 11:48:55] C45 0x0C1A = 0x0000
[2025-08-04 11:48:55] C45 0x0C30 = 0x3056
[2025-08-04 11:48:55] root@zynqmp-iwg36o:~#

0 Evan Mayhew 1 month ago in reply to Madhusankar SP

TI__Mastermind 24988 points

Hi Madhusankar,

I see in both dumps, the PHY's configuration is correct and link is up. The main difference between configurations is seen in register 0x12 - interrupts enabled for interrupt polling mode. From PHY perspective, I don't expect any communication failure in either case.

There is some SoC state machine dependency regarding interrupts. Could you please open a new thread targeted at SoC for debug support on this log?

Madhusankar SP said:
[2025-07-15 10:37:54] [   21.798104] audit: type=1327 audit(1709054777.744:2): proctitle="(systemd)"
[2025-07-15 10:37:55] [   22.885989] irq 56: nobody cared (try booting with the "irqpoll" option)
[2025-07-15 10:37:56] [   22.892701] CPU: 0 PID: 741 Comm: systemd Not tainted 6.6.40-xilinx-g0b36ba42be64 #1
[2025-07-15 10:37:56] [   22.900447] Hardware name: xlnx,zynqmp (DT)
[2025-07-15 10:37:56] [   22.904623] Call trace:
[2025-07-15 10:37:56] [   22.907061] dump_backtrace+0x90/0xe8
[2025-07-15 10:37:56] [   22.910732] show_stack+0x18/0x24
[2025-07-15 10:37:56] [   22.914048] dump_stack_lvl+0x48/0x60
[2025-07-15 10:37:56] [   22.917711] dump_stack+0x18/0x24
[2025-07-15 10:37:56] [   22.921027] __report_bad_irq+0x38/0x120
[2025-07-15 10:37:56] [   22.924950] note_interrupt+0x310/0x360
[2025-07-15 10:37:56] [   22.928786] handle_irq_event+0xd8/0xe8
[2025-07-15 10:37:56] [   22.932623] handle_fasteoi_irq+0xb0/0x284
[2025-07-15 10:37:56] [   22.936720] generic_handle_domain_irq+0x2c/0x44
[2025-07-15 10:37:56] [   22.941347] zynq_gpio_irqhandler+0xa0/0x16c
[2025-07-15 10:37:56] [   22.945617] generic_handle_domain_irq+0x2c/0x44
[2025-07-15 10:37:56] [   22.950244] gic_handle_irq+0x6c/0x9c
[2025-07-15 10:37:56] [   22.953907] call_on_irq_stack+0x24/0x4c
[2025-07-15 10:37:56] [   22.957830] do_interrupt_handler+0x80/0x84
[2025-07-15 10:37:56] [   22.962014] el0_interrupt+0x50/0xd8
[2025-07-15 10:37:56] [   22.965590] __el0_irq_handler_common+0x18/0x24
[2025-07-15 10:37:56] [   22.970121] el0t_64_irq_handler+0x10/0x1c
[2025-07-15 10:37:56] [   22.974218] el0t_64_irq+0x190/0x194
[2025-07-15 10:37:56] [   22.977794] handlers:
[2025-07-15 10:37:56] [   22.980060] [<0000000076a29780>] irq_default_primary_handler threaded [<00000000a58e1e22>] phy_interrupt
[2025-07-15 10:37:56] [   22.989564] Disabling IRQ #56

The conditions for this interrupt failure are not clear to me.

Thank you,
Evan

Interface

Interface forum

DP83869HM: Phy detection inconsistency