DP83822I: Register Settings of DP83822

Hi, 

There is no way to adjust the slew rate. For RGMII, clock delay can be controlled by register, however. 

Best,
J

Thank you for your reply.

Is it possible to speed up the slew rate of Tf and Tr without using registers?

If the slew rate of Tf and Tr is slow in RGMII mode and communication errors occur, is it possible to eliminate the communication errors by controlling the clock delay?

Hi,

There is no on-chip solution to change the slew rate. 

Customers often configure clock/data delay to ensure that the data is sampled on the correct clock edge. This is because RGMII is an edge based protocol and the PHY provides both CLK and data to the MAC. 

Best,
J

Thank you for your reply.

Are there any application notes or guidelines for setting RGMII clock/data delays?

If so, please provide them.

best regards,

koki

Here's an additional question from a different perspective.

Are the MAC impedance control bits [4:1] in the IO MUX GPIO control register (IOCTRL) a register for changing the series termination value of the output signal inside the PHY?

How does changing the value of this register affect the output signal of the PHY?

Here's an additional question from a different perspective.

Are the MAC impedance control bits [4:1] in the IO MUX GPIO control register (IOCTRL) a register for changing the series termination value of the output signal inside the PHY?

How does changing the value of this register affect the output signal of the PHY?

Hi, 

I apologize but it looks like DP83822 has only one setting to control TX/RX delay to 3.5ns.

MAC impedance changes the internal termination on the MII side. Changing this value will affect the output signal by changing the differential impedance. Changing this may cause impedance mismatch on the PHY and the MAC.

Best,
J