SerDes data comms over 155Mbps single mode SFF LC transceiver

Greetings -

The '1023/1224 are nice generic Ser/Des type parts.  They collect up the 10 bit payload and add a coule of bits for the clock information into a single serial link.  If you send all 0's or 1's there is only one guaranteed transition.  For optical or other forms of isolation, DC Balance is usually needed.  If these 10bit parts are to be used, the system usually performs a 10b/8b code/decode before/after the SER/DES to make the transmitted signal DC Balanced. 

Alternately, you could consider the 8/10b based ser/des such as the fast ENET Fibre Transceivers, or other SERDES that provide some level of coding such as Channel Link 2. 

Selection of the Ser/Des usually comes down to requirements on the coding, Interconnect (length, type, channels), and the low-speed interafce (levels, width, speed).  TI has many Ser/Des families to choose from, please see the Ser/Des families listed in the TI product tree under the INTERFACE heading.

Best Regards;
John Goldie
DPS APPS / SVA
(Vacation alert = away until Jan 3, 2012)

Hi Karsten,

John is right that we have a pretty wide array of SerDes parts.  I can help you narrow them down, but I am little unclear on what you have in mind.  Do you have just two TTL data lines that you want to interleave and send over fiber?  Are these two lines synchronous with one another, and do they have an associated clock signal?  If so, what is the rate - 60 kbps?  Is this a transmit-only link, or do you need it to be bidirectional?

It's true that what we call "high speed interface" here tends to focus on signals in the gigabit range.  Our serializers tend to tend to accomodate wider parallel data buses (such as 8, 10, 16, or 20 bits) as well.  TI does have a group that focuses on industrial interfaces, though, and they can be reached here: http://e2e.ti.com/support/interface/industrial_interface/default.aspx.

For a lower data rate, have you considered just using an electrical interconnect rather than an optical one?  Converting the TTL signals to a differential standard such as RS-422 or RS-485 and transmitting them over copper might be a simpler or more economical solution.

Best regards,
Max Robertson
Analog Applications Engineer
Texas Instruments
m-robertson@ti.com

Hi,

thank you for your support. We have just the two data lines with a signal from DC up to max. 60kHz. These lines are not synchronous and have no associated clock signal. It is a transmit only link. The fiber is chosen because we have a harsh environment and we would like to have galvanic isolation (also for intrinsical safety). RS-422 etc. have the disadvantage that we need 4 copper wires (we have a spare fiber available) and we want to bridge a distance of >1km.

Ideally I would like to have a 8B/10B SerDes with an interface to our fast Ethernet single mode fiber transceiver. I think the Ethernet PHYs are more complicated to set up in our application because they use the MII interface (with usually additional 25MHz clock) and have a packet based transmission. We have the requirement to minimize latency (<20us) and jitter.

If I need DC balance for the transceivers it could also be an option to use the 8 unused bits of the 1023/1224 to achieve DC balance. Can you recommend a pattern for the unused  bits which speeds up receiver lock in auto sync mode?

Best regards

Karsten Schwinne

Hi,

thank you for your support. We have just the two data lines with a signal from DC up to max. 60kHz. These lines are not synchronous and have no associated clock signal. It is a transmit only link. The fiber is chosen because we have a harsh environment and we would like to have galvanic isolation (also for intrinsical safety). RS-422 etc. have the disadvantage that we need 4 copper wires (we have a spare fiber available) and we want to bridge a distance of >1km.

Ideally I would like to have a 8B/10B SerDes with an interface to our fast Ethernet single mode fiber transceiver. I think the Ethernet PHYs are more complicated to set up in our application because they use the MII interface (with usually additional 25MHz clock) and have a packet based transmission. We have the requirement to minimize latency (<20us) and jitter.

If I need DC balance for the transceivers it could also be an option to use the 8 unused bits of the 1023/1224 to achieve DC balance. Can you recommend a pattern for the unused  bits which speeds up receiver lock in auto sync mode?

Best regards

Karsten Schwinne

Karsten,

Are you able to supply a reference clock?  This will be a requirement for any SerDes device I know of, since some kind of clock is needed to be able to (1) generate the high-speed serial line rate and (2) latch in the parallel data.  Since there isn't a clock that is already associated with your data, you can use any clock that meets the device specs as long as it is much faster than the rate of the TTL data.  This ensures that transitions on the TLL signals are not missed.

For the 1023/1224, the fastest receiver lock time is when the device's synchronization pattern is used (111111000000).  This can be done by either setting the parallel bus to 1111100000 or by asserting the device's SYNC input.  Since there will be 8 unused bits, the best way to ensure DC balance would most likely be to provide true and complement (inverted) versions of each TTL signal.  The complement versions of the data could just be unused at the other end.  The remaining unused bits should be divided equally among ones and zeros.

If you require 8b/10b encoding, the TLK1501 may work.  It is a general gigabit SerDes with internal 8b/10b encoders and decoders.  It does have an Ethernet-style parallel interface with TX_EN and TX_ER controls, but in your application you would most likely only need to use TX_EN to set up the link (it sends special reserved codes that enable synchronization of the receiver).  It is just a physical layer device and does not have any requirements in terms of packet transmission.

Best regards,
Max Robertson