SN75LVDS83B: HDMI/DVI to LVDS Converter

Hi Mustafa,

What is the pixel clock rate of your required 2K resolution? It would help if we had an exact pixel clock rate for this display resolution.

Pixel clock rate = Horiztontal total * Vertical total * frames per second


You may have seen the app note about HDMI/DVI to LVDS/OLDI: https://www.ti.com/lit/an/slla325c/slla325c.pdf
And you are right that the solutions would not cover common 2K resolutions.

Alternatively, if your pixel clock rate is below 170 MHz, you could also use the DS90UB949-Q1 (HDMI serializer) with a LVDS deserializer such as the DS90UB948-Q1.

Best regards,
Ikram

Hi Ikram,

My pixel clock rate would be 2560x1440x45=165.888.000 that makes 165.89MHz which is lower than 170MHz. Therefore, I believe if I reduce my frame per second expectation from 60 to 45, I will be able to achieve my goal.

I also found DS90UH949A-Q1 (HDMI serializer, max rate: 210MHz) and DS90UH948-Q1 (LVDS deserializer, max rate: 192 MHz). By using those components, I might increase my fps a little more, I guess. Am I right?

Thank you for your time,

Mustafa

Hi Mustafa,

Is 2560 x 1440 the horizontal x vertical active or total? I suspect it might be the active video resolution.
To find PCLK you would need to use the horizontal total x vertical total where Total = Active + front porch + back porch + sync width.

For example, with common 1920x1080p resolution:

# THW = Horizontal Total Pixels = AHW + HBP + HFP + HSW
# TVW = Vertical Total Lines = AVW + VBP + VFP + VSW
# AHW = Hoizontal Active Pixels
# AVW = Vertical Active Lines
# HBP = Horizontal Back Porch Pixels
# VBP = Vertical Back Porch Pixels
# HSW = Horizontal Sync Width Pixels
# VSW = Vertical Sync Width Lines
# PCLK = Pixel Clock Rate in MHz
# Bits_per_pixel = 18, 24, or 30 


THW[0] = 2200
TVW[0] = 1125
AHW[0] = 1920
AVW[0] = 1080
HBP[0] = 148
VBP[0] = 36
HSW[0] = 44
VSW[0] = 5
HFP[0] = 88
VFP[0] = 4
PCLK[0] = 148.5
Bits_per_pixel[0] = 24


Please check the PCLK rate using the total values, and also check the display datasheet for LVDS clock and frames per second limitations. The display panel datasheet usually has the min/max values for each.

And yes, you would need to ensure the devices used all support the PCLK rate for the application. 
For example, with the 949A and 948 pair, you can use up to 192 MHz. 

Best regards,
Ikram

Hi Ikram,

Thank you for clarification. Based on my calculations I will be able to achieve around 45Hz which is fine by me. I wonder even if the pixel clock rate would be sufficient, is it wise to use SERDES architecture for simple conversion? As far as I know it is designed to propagate signals to far distances without distortion. In such small distances is it an efficient converter? 

Hi Mustafa, although FPD-Link SerDes mentioned are typically used over cables, it will work over short distance as well.