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DP83869HM: Disable Internal loopback, enable RX Spoofing and Disable TX line

Balaji TS2
Intellectual 280 points

Part Number: DP83869HM

Tool/software:

Greetings for the day,

I have raised a query(link is mentioned below) few months back related to Optical RX Spoofing and I got clarification for my query. In the query we have suggsted to Set Bit 15 of register D4 to enable Optical RX Spoofing, which was successful. But that solution is creating another problem i.e. internal loopback. We are getting back copy of data which we have sent. Which should not happen. 

So my question is how to disable internal loopback and enable only RX Spoofing?

And one more thing is there any way to disable TX line of Opticl port.

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1486964/dp83869hm-keep-copper-port-link-status-unchanged-when-optical-port-link-goes-down/5757005?tisearch=e2e-sitesearch&keymatch=%2520user%253A476365#5757005

Thank You.

Regards,

Balaji TS

  • 0
    TI__Mastermind 40935 points

    Hi Balaji,

    As you are operating in a way the device was not intended for, the suggested mode was a workaround to see what is capable with the device. 

    As you had mentioned, you are engaging the device in one-way communication where MDI is uni-directional. The setting provided is able to create uni-directional link by causing the PHY to link up with itself, which ungates the state machine to send data out on MDI.

    The behavior you are observing where TX data is observed is an artifact of this. However, as you wouldn't be expecting anything on the line in general, would it make sense to either ignore or design out the RX bus-line on RGMII?

    Regarding disable TX line of optical port, you may disable internal loopback (Reg 0xD4[15]), which would place you back where device not linkup in this configuration.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Intellectual 280 points

    Hi Gerome,

    Thank You for the response.

    Gerome Cacho said:
    design out the RX bus-line on RGMII?

    As we already have the fabricated board it might be difficult to remove RX bus-line on RGMII. So is there any register setting to disable the RGMII Rx line/TX line or disable RGMII RX/TX line clock?

    And incase if we remove Rx busline of RGMII, the Electrical port link won't be affected right? We are working in 100M and 1000M media conversion mode.

    Regards,

    Balaji

  • 0 in reply to Balaji TS2
    TI__Mastermind 40935 points

    Hello Balaji,

    Typically MII Isolate (Reg 0x0) disables the RX lines. This setting is typically used for EMC debugging (think RE), but this could actually help in your specific application.

    Regarding board spin, connection of RGMII lines have no bearing on MDI linkup.

    Sincerely,
    Gerome

  • 0 in reply to Gerome Cacho
    Intellectual 280 points

    Hi Gerome,

    As per the suggesion I made 0x00[10] = 1 to enable MAC isolation but still we are facing internal loopback. 

    As we are working in media conversion(Electrical to Optical) mode, we don't have RGMII lines in our hardware. We have only RJ45 Bi-directional lines at electrical side. And we are facing loopback at RJ45 side only.We cannot design out any lines at RJ45 port as we don't have seperate lines for TX and RX.

    Below is our Hardware Setup, where we have 2 device, TX and RX. PC1 is connected to RJ45 port of TX device. I have enable RX Spoofing in TX device by setting 0xD4[15] which is causing loopback to RJ45 port. So is there any way to drop the packets which are sending back to RJ45 port from TX device(DP83869HM TX).

    Thank You.

    Regards,

    Balaji TS

  • 0 in reply to Balaji TS2
    TI__Mastermind 40935 points

    Hello,

    Unfortunately, we do not have a way to disable half of the CU. You may look to create custom CAT5e cabling in your application to bypass this constraint as a system workaround.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Intellectual 280 points

    Hi Gerome,

    We have tried using custon CAT5e cable but it was not successful as we don't have specific TX and RX lines at CU as I mentioned earlier. Below are our CU pins.

    Is there any datasheet to understand more about internal loopback (which is getting enabled using 0xD4 bit 15) and know about D4 register and other unkown registers?

    Kindly help us to resolve this issue as the internal loopback causing inappropriate behaviour in our application. 

    Thank You.

    Regards,

    Balaji TS

  • 0 in reply to Balaji TS2
    TI__Mastermind 40935 points

    Hello,

    The only information I can provide is that this bit is able to trigger an internal loopback which is fooling the FX state machine that there is valid RX (while it is disconnected physically). This is a necessary step as FX typically needs the RX to establish stable link but is being bypassed in your application.

    I would see if there is a way in your end use case to ignore the incoming data on the transmitter side of the MC chain.

    Sincerely,

    Gerome