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TCAN4550: SDO negative spike while enabling nCS

Zion Twig
Prodigy 30 points
Part Number: TCAN4550

Tool/software:

Hi,

On TCAN4550 we have the following negative spike on SDO while enabling the nCS as shown below.

According to spec this pin is high impedance until the SPI output is enabled via nCS.

Is there some register setting which prevent this negative spike? 

Thanks,

Zion.

  • 0
    TI__Mastermind 32970 points

    Hi Zion,

    There are no register configurations for the SPI interface.

    From the datasheet, the Chip Select Setup Time (tcss) is a minimum of 28ns, meaning that the we would expect to see the SDO pin transition from a Hi-Z state to a Driven state within 28ns after the nCS pin transitions Low.  According to your time scale with 40ns/div, this appears to occur in the time frame of this state change. 

    I noticed that your SDO waveform is High while nCS is also High, meaning there must be some external pull-up source on the SDO pin to keep it High while the SDO pin is in a Hi-Z state.  This pulse may be due to some charging capacitance and inrush current during this transition, but because data is sampled based on the falling clock edge, this pulse so close to the nCS transition would not result in a data sampling error.

    Regards,

    Jonathan