DP83822I: Power Sequence Support Needed

Hi J,

Thanks. As the customer is using 2.5V for MAC interface, the VDDIO is set to 2.5V.

They determined to ramp VDDIO and AVD at the same time.

Best regards,

Kazuki Itoh

Hi Itoh-san,

Great to hear! Let me know if the customer has additional questions.

Best,

J

Hi J,

I have a couple of questions from the customer.

1. How the T1: ±100ms is determined? Is that measured by 50% of the each rail?
   
2. If yes, it looks like the ramp up at the same time is allowed because it is within ±100ms T1 range.
   Given that, AVD (3.3V) ramps up before VDDIO(2.5V) in my customer's design.
   Is it still okay? Could you please review the waveform below?
   
3. Could you let me know the current and power consumption of VDDIO=2.5V and AVD=3.3V respectively?
   It's not found on Table 10-1 with this combination.

Best regards,

Kazuki Itoh

Hi Itoh-san, 

1. That is correct. 
2. The waveform except that there is a initial ramp of 1V for 2.5V is good. Please ensure that the customer can follow both VDDIO<AVD+0.3V and simultaneous ramp up if possible. 
3. I couldn't find this data on our end.

Please let me know. 

Best,

J

Hi J,

About #2, yes, there's initial 1V ramp, but it's still within T1=±100ms specified in the datasheet. Is it not allowed?

About #3, my customer is reffering to Table 10-1 Power Supply Characteristics. However, my customer would like to provide the data under  VDDIO=2.5V and AVD=3.3V. Does it make sense?

Best regards,

Kazuki Ioth

Hi Itoh-san, 

2. Yes, timing is fine. I am talking about this comment in the datasheet:
AVD and VDDIO potential must not exceed 0.3 V prior to supply ramp.

especially when AVD is not ramped at all to prevent false detection. 

3. I understand you need 2.5V VDDIO and 3.3V AVD. Unfortunately, we couldn't locate the data and it will have to be collected. This will most likely take couple of weeks.

Please let me know. 

Best,
J

Hi J,

Thank you.

> Unfortunately, we couldn't locate the data and it will have to be collected. This will most likely take couple of weeks.

My customer is requesting us to collect the data. It is okay even if it takes a couple of weeks.

Could youp please support?

Best regards,

Kazuki Itoh

Hi Itoh-san, 

We can support this. However, please note that US has Fourth of July holiday so US office will be closed. 
After we come back from the holiday, we expect collecting data will take two weeks since we do not have power consumption set up currently in the lab. 

I will keep you updated. 

Best,
J

Hi J,

Thank you for taking an action on this. I have one more question.

Should the power sequence strictly be followed even if the DP83822's RESET_N pin is Low by external pull-down and RESET_N goes high after VDDIO and AVD fully ramping up?
My customer guesses that the IO pins including hard strap doesn't operate unless RESET_N pin goes high so the false detection can be avoided.

Best regards,

Kazuki Itoh

Hi Itoh-san, 

We recommend to follow the power sequence even when the RESET_N pin is low since the recommendation was given out considering that the the reset signal will be low. But, the customer's understanding is correct that the strapping doesn't sample until RESET_N goes high. 

Best,
J

Hi J,

It still doesn't make sense to me.

Why do you recommend to follow the power sequence when RESET_N is low while the strapping doesn't sample until RESET_N goes high?

Could you please make it more clear?

Best regards,

Kazuki Itoh