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Inconsistent or loss of data transfer from the PC to the System.


PC ---------->TUSB3410 ------->MSP430-------->Serial flash



1) In this system to synchronize with the Application  we are adding the
delays in the Application,
Is there any other way to take care of the synchronization problem as the
delays are different for various PC and laptops?
We are currently using synchronous call.

2) We need to transfer the data from the PC to the TUSB Bulk end point using
read and write WIN32API, after the read and write we are clearing the port.
2a) Need clarification on the  PC to TUSB transfer ,
When the TUSB  data buffer is full will it send the signal to the PC side to
stop sending the next data, until it clears the current data or will it
overwrite the TUSB data buffer with the incoming data ?
2b) Driver is configuring the bulk pipe for communication, will there be any
data loss (even if it is single byte) ?

2c) How many messages TUSB can buffer ?  If the message size is one byte


System consists of the  TUSB3410 interfaced to MSP430.

Data transfer (Read and Write) happens from the PC to the TUSB3410 which is
connected to MSP430 through UART port, from the MSP430 buffer(RAM 2K and the
buffer size is 256bytes) it is written to the serial flash via SPI .

MSP 430 is working at 12 MHz
Baud rate settings of the UART port is 460800
  • Hello,

    1) Could you please clarify wich type of sync you need? tipically, the USB to serial conversion takes care of the sync within the 3410's bootcode (wich is hardcoded in the chip).

    2a) I suggest taking a look at "6.2 Bulk Data I/O Using the EDB" of our 3410's spec in order to clarify any Rx/Tx features from bulk EP tranfers.

    2b) There shouldn't be any data loss on normal conditions. In case you want to avoid an error, you can monitor "LSR: Line-Status Register (Addr:FFA5h)" and see if any DMA transfer was halted. 

    2c) The receiver data register consists of a 32-byte FIFO. Data received via the SIN terminal is converted from serial-to-parallel format and stored in this FIFO. Data transfer from this register to the RAM buffer is the responsibility of the DMA controller (2K × 8 shared RAM used for data buffers and endpoint descriptor blocks (EDB))