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TMDS1204: What are the recommended register settings for the TMDS1204?

Masamichi Higashimoto
Prodigy 30 points
Part Number: TMDS1204

Tool/software:

We designed an HDMI input/output board using a combination of the TMDS1204 and an AMD FPGA.
The HDMI compliance test was conducted by the HDMI certification body and the following FAILs were noted.

  No.1 OUTPUT Test ID 7-4 TMDS - Trise, Tfall
           The rise and fall times of Data0, Data1, and Data2 when outputting 3840x2160@30p signals are less than 70 ps compared to the spec of 75 ps or more.

            From the TMDS1204 datasheet, I believe that this can be handled by changing the SLEW_3G_Register setting, am I correct?

            If possible, please let me know the results of your evaluation of how much changing the SLEW_3G_Register setting changes the rise and rise time when outputting 3840x2160@30p.

  No.2 INPUT Test ID 8-7: TMDS – Jitter Tolerance

            Only the 27M Type 2 27MHz (JAE) configuration FAILed, while the 27M Type 1 Cat1+Cat2 (Agilent) configuration and 74M, 148M, 222M, 297M PASSED.

            Initially, I thought that the FPGA lacked jitter tolerance, so I contacted AMD, but they assured me that the FPGA would not be able to receive the data without jitter cleaning with Redriver.

            I referred to the datasheet but could not find a good setting to increase jitter tolerance at low transmission rates. Please let me know what to try.
 

  • 0
    TI__Guru**** 178126 points

    Hi,

    Can you please share your schematic, layout, and register dump?

    On the Trise and Tfall, similar question was asked in the past, please see this e2e thread for my response.

    TMDS1204 being a re-driver, can only compensate the ISI-related jitter. It can not compensate random jitter, it will pass through the random jitter. Have you tried to tune down the TMDS1204 EQ or using the TMDS1204 AEQ and see if it helps with the RX jitter tolerance?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 30 points

    Hi David-san

    Thank you for your reply.

    The question on the Time-rise and Time-fall from Hayashi-san in TIJ is what I asked him.

    There is a significant discrepancy between the measurements you shared and the measurements we took.

    Our circuit is DC-coupled, but we mistakenly set TX_AC_EN=‘1’, so we plan to remeasure after correcting it.

    Now, let's move on to the next issue.

    The TMDS1204 data sheet contains the following description.
    The TMDS1204 supports adaptive equalization (AEQ) for HDMI 2.1 FRL.It does not support AEQ for HDMI 1.4 or 2.0.

    What we want to improve is the RX jitter torelance at low bit rates in HDMI 1.4.

    You suggested tuning down the TMDS EQ settings, but please tell me the specific registers.

    For reference, please find attached the test procedure manual for Test ID 8-7: TMDS - Jitter Tolerance.
    I don't know how to attach files, so I'm posting a screenshot.

    Best regards

    Higashimoto

  • 0 in reply to David (ASIC) Liu
    TI__Guru**** 178126 points

    Higashimoto-san

    The TMDS1204 has three sets of CTLE curves (3Gbps CTLE, 6Gbps CTLE, and 12Gbps CTLE) with each curve having 16 AC gain settings and 3 DC gain settings.  The expectation is Map A and C should be used if TMDS1204 is used in a source application and Map B for a sink application.

    For the CTLE selection, this is register 0x0E as shown below.

    For each lane EQ, they are register 0x15h, 0x17h, 0x19h. Please note there is no EQ for the CLK lane when in the TMDS mode.

    Thanks

    David