DP83867IS: Power Sequence at Twe-Power Supply Config

Hi Hiroshi-san,

user5163865 said:

1. In the case of a two-power supply configuration, I think power sequencing is not necessary. Is this correct?

This is correct. 

user5163865 said:

2. When VDD1P0 (VCC_1.0V) is applied, there is a voltage shift of about 250mV before VDDIO (VCC_1.8V) is turned on. Is this a problem?
If VDD1P0 is not applied, there is no voltage shift, so this is probably a leakage voltage from inside the IC.

3. There is a voltage shift of 650mV from the start of the PL_3.3V power supply, another power supply on the board, until VDDIO (VCC_1.8V) rises. Will this have any effect on ETH-PHY?

As long as the RST_N is low until the device fully powers up, this power sequence should be fine. 

Please let me know if you have any other questions. 

Best,
J

Hi J-san,

Thank you for your support.

We have checked the customer's control of power supply startup.

Currently, due to a circuit problem, we are unable to fix RESET_N low when the power is turned on.
The reset is controlled by the FPGA, and a high signal is output for irregular periods.
This occurs before the device has fully started up.

We apply a reset after the IC has started up before using it, but as you stated in your initial answer, is it necessary for RST_N to be low until the device has fully started up?

Best regards,
Hiroshi

Hi Hiroshi-san,

It is recommended to pull RST_N low while the power is being ramped per datasheet especially the device can get stuck in a bad state when the device is initialized without clock signal. 

What problem is the customer currently having?

Best,
J