Tool/software:
Hi Team,
Can you help to review below sch and layout? Thanks!
There will be 3 solutions applied in one project.
Hi Kailun,
For all the boards:
1) The RS485 traces should be impedance matched to the expected cable's characteristic impedance (RS485 usually uses 120 ohms but cat5 cables for example use 100 ohms).
2) The RS485 traces should be length matched (especially board23). You want the distance from the device's pin to the board connector to be the same length for A and B pins.
3) keep A/B traces following each other in parallel when you can, they are differential pins and can be used to cancel out EMI if they are closer to each other
Board23:
Potentially has a weak GND'ing because it goes through a skinny metal layer on the top. I would recommend trying to move the 3.3V trace to stop it from choking the GND pin and maybe add more GND vias closer to the GND pin of our device.
Pin 8 is the Vcc pin, you have decoupling caps on the schematic but I don't see them next to the actual pin.
Board 14:
I recommend breaking the top trace here (the red) and then placing a via(orange) to the left of the split. For decoupling caps, you want to avoid 'T' or 'Y' splits. Having a Y/T connection makes the cap less effective.
-Bobby
Hi Kailun,
One minor layout suggestion. (Will probably still work without the change but I still recommend trying to make GND cleaner)
They can probably shift the traces up and to the right to make more room for the GND plane (trace is kind of skinny).
Add more vias near the GND pad to provide lower inductance. (I denoted them as red dots below)
We want to try to make GND path to the pin as less resistive as possible.
-Bobby
