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Original question:

TSWDC155EVM: TSWDC155EVM with ADC3683EVM

TSWDC155EVM: Data capture from ADC3683EVM using TSWDC155EVM

NISHANT GUPTA
Prodigy 160 points
Part Number: TSWDC155EVM
Other Parts Discussed in Thread: ADC3683EVM,

Tool/software:

Hi,
Thanks to @Rob Reeder for providing the required FM/SW/User guide; I am now able to capture data from ADC3683EVM using TSWDC155EVM.
The setup comprises of:
a) ADC3683EVM connected to PC using USB cable
b) Internal CLK and DCLK on ADC3683EVM
c) TSWDC155EVM connected to PC using Xilinx DLC10 JTAG cable
d) Software used: msps server (Refer Fig. E1.png & E3.png) and ADC3683EVM (Refer Fig. E2.png) python client for user configuration and data capturing
Though I am able to acquire the data with the above setup; Currently, I am facing the following issues while capturing data:
1) The data capture is too slow. It takes about 30 seconds to get 30k samples (Refer FIG. E2.png). Can I make it faster, may be less than a second? What changes do I need to do?
2) I do not know how to capture triggered event or set threshold to start the capture
3) I could not capture the Triangular pattern data. Only a flat line was obtained.
Kindly advise to resolve the above issues.

Fig. E1

Fig E2

Fig E3

Thanks & regards,
Nishant

  • 0
    Prodigy 160 points

    Dear TI Team,

    Kindly respond to the queries mentioned in my above post, repeated below for convenience:

    1) How to make the data capture faster with the given setup (ADC3683EVM with TSWDC155EVM)?

    2) How to capture a Triggered event or using Threshold on the analog input signal?

    3) How to capture the Triangular pattern, provided on ADC3683EVM?

    Please let me know the changes required in the hardware and/or the code  to resolve these issues.

    Thanks & regards,

    Nishant

  • 0 in reply to NISHANT GUPTA
    TI__Intellectual 1440 points

    Hi Nishant,

    Questions 1 and 2 pertain to the FPGA capture baord and Firmware. I have looped in our FPGA engineer to answer these questions.

    Regarding your third question, are you referring to the ramp pattern generated by the ADC? If so, please share how you are configuring the adc into this mode.

    Best,

    Luke Allen

  • 0 in reply to Luke Allen
    TI__Intellectual 2340 points

    Hi Nishant,

    The FPGA design currently operates only on SW triggered data capture as the primary goal is evaluation of the converter performance. Threshold based or external HW event based triggering is not implemented because our customers usually prefer to build their own designs (with the EVM connected to a different devKit or proto board) for testing such features.

    The design data offload is slow because it happens over JTAG, and we have plans to release a new version of the DC155 FPGA card that will enable offload over the USB3 interface. Kindly try increasing the JTAG speed (this can be done through Vivado HW manager by editing the parameters of the cable). Setting the JTAG speed to the max supported by the cable will help reduce the offload time.

    Regards,
    Ameet