• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 99 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

DVI Dual Link Receiver

TFP401: DVI dual-link

Andrzej Głód
Prodigy 10 points
Part Number: TFP401

Tool/software:

I have a question regarding dual-link DVI, which is not officially supported by TI.

However, since the integrated circuit we have been using for years is now obsolete, we are preparing a replacement solution — possibly using two TFP401 devices.

According to the DVI specification, HSYNC and VSYNC signals are carried only on TMDS channel 0. Therefore, we are concerned whether the second TFP401, which would be connected to TMDS channels 3, 4, and 5, and consequently would not receive any HSYNC or VSYNC signals, will still provide valid video output on its pixel interface.

We are aware of Application Note 5123, "Dual Link DVI Receiver Implementation", but it does not address this particular issue.

  • 0
    TI__Guru**** 177676 points

    Hi,

    The TFP401/401A discriminates between valid pixel TMDS characters and control TMDS characters to determine the state of active display versus blanking (for example, the state of DE). 

    So the second TFP401/401A, connected to TMDS channels 3, 4, and 5, will still see valid pixel TMDS characters, and determine the display is active.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 10 points

    Dear David,

    Thank you very much for your prompt and helpful response.

    To make sure I understand the behavior correctly, I’ve attached a timing diagram showing the expected output signals from the second TFP401 (the one connected to TMDS channels 3, 4, and 5).

    Could you please confirm if this reflects the actual behavior of the pixel output interface from the second TFP401?

    Thank you again for your assistance!

  • +1 in reply to Andrzej Głód
    TI__Guru**** 177676 points

    Hi,

    For the second TFP401, your understanding is correct.

    Thanks

    David