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SN65DSI86: *ERROR* Link training failed, link is off (-5)

Clement hsu
Prodigy 10 points
Part Number: SN65DSI86

Tool/software:

Hi,

We are porting this IC on iMX95 platform, but met errors on kernel boot up:

==================================

[ 4.772672] ti_sn65dsi86 7-002d: [drm:ti_sn_bridge_atomic_enable] *ERROR* Can't read lane count (-110); assuming 4
[ 4.777219] imx6q-pcie 4c300000.pcie: iATU: unroll T, 128 ob, 128 ib, align 4K, limit 1024G
[ 4.781602] imx6q-pcie 4c380000.pcie: iATU: unroll T, 128 ob, 128 ib, align 4K, limit 1024G
[ 5.028699] ti_sn65dsi86 7-002d: [drm:ti_sn_bridge_atomic_enable] *ERROR* Can't read eDP rev (-110), assuming 1.1
[ 5.154858] ti_sn65dsi86 7-002d: [drm:ti_sn_bridge_atomic_enable] *ERROR* Can't read max rate (-110); assuming 5.4 GHz
[ 5.378389] ti_sn65dsi86 7-002d: [drm:ti_sn_bridge_atomic_enable] *ERROR* Link training failed, link is off (-5)

===================================

This is the i2cdump:

Read EDID show nothing.

What this error means? what's next action to fix this? thank you~

  • 0
    TI__Mastermind 22830 points

    Hi Clement,

    Could you please check whether the initialization sequence is following the sequence described in the datasheet "8.4.2 Power-Up Sequence". From your error list it shows errors that it cannot read the lane rate, lane count. Which link training mode are you using?

    Please try test pattern generation to check whether the programmed timing can successfully display to the panel. This will verify whether the DP output and display configurations are working. To generate the register writes for this, please use the calculator tool shared here: [FAQ] SN65DSI8x Programming Tools

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Prodigy 10 points

    Hi,

    Yes, I tried to generate test pattern to panel by i2c command, and test pattern can show test pattern correctly.

    Now, I'm turning back to driver part, looks the error happened on training stage.

    I traced the driver code, it set training as "Semi auto link training mode", but Link is always in OFF mode.

    The code piece on driver is:

        /*
         * We'll try to link train several times.  As part of link training
         * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER.  If
         * the panel isn't ready quite it might respond NAK here which means
         * we need to try again.
         */
        for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) {
            /* Semi auto link training mode */
            regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
            ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
                               val == ML_TX_MAIN_LINK_OFF ||
                               val == ML_TX_NORMAL_MODE, 1000,
                               500 * 1000);
            if (ret) {
                printk("clement - Training complete polling failed");
                *last_err_str = "Training complete polling failed";
            } else if (val == ML_TX_MAIN_LINK_OFF) {
                printk("clement - Link training failed, link is off");
                *last_err_str = "Link training failed, link is off";
                ret = -EIO;
                continue;
            }

            break;
        }

    My error log:

    [ 4.771881] ti_sn65dsi86 7-002d: [drm:ti_sn_bridge_atomic_enable] *ERROR* Can't read lane count (-110); assuming 4
    [ 4.898212] clement - pdata->dp_lanes = 2
    [ 4.898217] clement - dp_lanes = 32
    [ 5.018360] ti_sn65dsi86 7-002d: [drm:ti_sn_bridge_atomic_enable] *ERROR* Can't read eDP rev (-110), assuming 1.1
    [ 5.138319] ti_sn65dsi86 7-002d: [drm:ti_sn_bridge_atomic_enable] *ERROR* Can't read max rate (-110); assuming 5.4 GHz
    [ 5.145728] clement - Link training failed, link is off
    [ 5.152753] clement - Link training failed, link is off
    [ 5.159861] clement - Link training failed, link is off
    [ 5.167003] clement - Link training failed, link is off
    [ 5.174136] clement - Link training failed, link is off
    [ 5.181252] clement - Link training failed, link is off
    [ 5.188395] clement - Link training failed, link is off
    [ 5.195553] clement - Link training failed, link is off
    [ 5.202670] clement - Link training failed, link is off
    [ 5.209777] clement - Link training failed, link is off
    [ 5.217411] clement - Link training failed, link is off
    [ 5.224551] clement - Link training failed, link is off
    [ 5.232010] clement - Link training failed, link is off
    [ 5.239144] clement - Link training failed, link is off
    [ 5.246686] clement - Link training failed, link is off
    [ 5.253841] clement - Link training failed, link is off
    [ 5.260976] clement - Link training failed, link is off
    [ 5.268089] clement - Link training failed, link is off
    [ 5.275222] clement - Link training failed, link is off
    [ 5.282347] clement - Link training failed, link is off
    [ 5.289991] clement - Link training failed, link is off
    [ 5.297527] clement - Link training failed, link is off
    [ 5.304764] clement - Link training failed, link is off
    [ 5.311874] clement - Link training failed, link is off
    [ 5.319010] clement - Link training failed, link is off
    [ 5.326143] clement - Link training failed, link is off
    [ 5.333256] clement - Link training failed, link is off
    [ 5.340388] clement - Link training failed, link is off
    [ 5.347531] clement - Link training failed, link is off
    [ 5.354669] clement - Link training failed, link is off
    [ 5.354765] ti_sn65dsi86 7-002d: [drm:ti_sn_bridge_atomic_enable] *ERROR* Link training failed, link is off (-5)

    What the training fail means? 

    My kernel is 6.6.36, the TI driver is inbox on NXP's BSP, not sure if this driver need to be updated? 

  • 0 in reply to Clement hsu
    TI__Mastermind 22830 points

    Hi Clement, 

    If the test pattern is working with the display, then it must be successfully link training with the DP/eDP display.

    Could you check whether the DP lane rate and number of lanes programmed are compatible with the display DP interface? Please also share your lane rate and lane count. The datasheet h"8.4.5.7.4 Semi-Auto Link Training" section described the link training process. 

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Prodigy 10 points

    Hi,

    Our panel spec is pixelclock=533.28Mhz, 3840x2160@60p., but it will cause fail on TI calcu excel file,

    So we use 266.64Mhz which is 30p, but panel show only some noisy, no correct image.

    We try to use pixelclock=76.42Mhz, 1366x768@60p which is another panel's parameter, it can show the image but of course not correct size as below.

    How we should set the pixelclock for 3840x2160 panel?

  • 0 in reply to Clement hsu
    TI__Mastermind 22830 points

    Hi Clement,

    Here is an FAQ about the resolution for the DSI86: [FAQ] SN65DSI86: Can DSI86 support 4k2k 60Hz?

    The maximum resolution is limited by the DSI data lane rate: which is maximum 1.5 Gbps per lane, and total 12 Gbps over 8 data lanes.

    The resolution you shared with 533.28 MHz PCLK is beyond the limits, because with 24 bpp, that is ~12.8 Gbps.
    As mentioned in that FAQ, you could consider using 18bpp instead of 24 bpp is the panel specifications allow this.

    Also, you could refer to the panel/display specifications to check whether the PCLK rate can be lowered by reducing blanking, or frame rate, or pixel depth (bpp). Could you share the panel specifications datasheet with us, so we can check the display timing tolerances? 


    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Prodigy 10 points

    Hi,

    Attached the panel spec.

    Another point is what's the dsi clock we should set from CPU side,

    On imx95 device tree:

    This's the 1366x768 clock setting, but we can not find a right setting for this 4K panel, CPU vendor suggest we need to check with TI for what's the correct pixelclock?

    assigned-clock-rates = <0>, <pixelclock*9>, <pixelclock*5>

    TFT-LCD Approval Specification Spec_N133DCE-GP1 ver 2.0.pdf

  • 0 in reply to Clement hsu
    TI__Mastermind 22830 points

    Hi Clement,

    As you can see in the display specifications you shared, the DCLK or pixel clock clock frequency is minimum 530.62 MHz, which is above what the resolution limit and DSI data limit is for the DSI86.

    The pixel clock frequency = Htotal * Vtotal * frames per second. Which at the display typical = 4000 * 2222 * 60 = 533.280 MHz.
    The total video data bandwidth = PCLK * bits per pixel = 533.280 MHz * 24 = 12.799 Gbps

    As we mentioned before, the DSI86 can only support up to 12 Gbps (which is 1.5 Gbps per DSI data lane, over 8 lanes maximum).

    This display panel resolution cannot be supported by the DSI86 based on the display specs shared. Please check if the display can support lower resolutions in alternative applications, or if there is a different display with lower refresh rate and PCLK rate which can be used instead.



    Also, just for your information, to find the DSI clock rate required, you can use this equation:
    DSI clock frequency = (PCLK frequency * bits per pixel)/ (2 * number of DSI lanes)

    Here are some examples with similar devices, which support LVDS instead of DP/eDP: [FAQ] SN65DSI84: SN65DSI83, SN65DSI84, and SN65DSI85 resolution guide 


    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Prodigy 10 points

    Based on this reply, can I use 18bpp with 533.28 MHz PCLK?

    Looks if download size from 24bpp to 18bpp, it will not exceed the TI spec.

  • 0 in reply to Clement hsu
    TI__Mastermind 22830 points

    Hi Clement,

    Yes, if you use 18bpp, then the video bandwidth will be = PCLK * bits per pixel = 533.280 MHz * 18 = 9.59904 Gbps, which is within the DSI86 specifications.

    To program this, please use the calculator tool we linked earlier. You can use it to enter the specifications to configure DSI and DP, and use test pattern for initial testing.

     [FAQ] SN65DSI8x Programming Tools 


    Best regards,
    Ikram