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TCAN4550: Confusion about RF0N Rx FIFO 0 New Message

mike f
Prodigy 100 points
Part Number: TCAN4550

Tool/software:

Hello, I see that a RF0N bit exists in both the MCAN Interrupts (address = h0824) and Interrupt Register (address = h1050) registers. What is the difference between the two? Do both need to be cleared (set to 1) after Acknowledging FIFO 0? I am using a driver that was supplied by TI and it does not include the h0824 register in the register map. I know this driver may not be perfect but it still concerns me.

Can someone please help me to decode the below paragraph about h0824 from the datasheet?

"8.6.3 Interrupt/Diagnostic Flag and Enable Flag Registers: 16'h0820/0824 and 16'h0830

This register block provides all the interrupt flags for the device. As the M-CAN interrupt flags 16'h0824 are described in 16'h1050 MCAN register description section and will be shown here but need to go to 16'h1050 for description. 16h’0830 is Interrupt enable to trigger an interrupt for 16'h0820."

Thank you!

-Mike

  • 0
    TI__Mastermind 33440 points

    Hi Mike,

    Register 0x0824 is a Read-Only copy of register 0x1050 that is adjacent to the other device (non-MCAN) interrupt bits in register 0x0820. 

    By placing a read-only copy of the MCAN interrupt register next to the device interrupt register allows both registers and ALL interrupt bits to be read in a single SPI read with the Length field set to 2 to increase the efficiency and reduce the time needed to read the interrupt registers.

    The MCAN interrupt bits can be read from either 0x0824 or 0x1050, but they can only be cleared by writing a '1' to the bits in register 0x1050.

    As a further decode that may help your overall understanding of the register map, I will point out that there are three groups of registers with different address ranges.

    The first range of registers (0x0000 - 0x000C) is for the Device ID and SPI Interface FIFO.  These registers do not require the crystal or high-speed (20MHz, or 40MHz) clock and only require the SPI clock to return a value.

    The second range of registers (0x0800 - 0x083C) are device configuration and interrupt flags that are not part of MCAN.

    The third range of registers (0x1000 - 0x10FC) are directly from the MCAN IP developed and licensed by Bosch.  These registers are unchanged from Bosch's IP with one exception in that an offset of 0x1000 has been added to each register address.  For example, the MCAN Control register in the TCAN4550 has an address of 0x1018 but an address of 0x018 in Bosch's documentation such as the M_CAN User's Manual (Link).

    As you can see, the MCAN Interrupt register 0x1050 is in the middle of the MCAN register block and it would require 2 separate SPI reads to read both the device related interrupts and the MCAN interrupts without providing a read-only copy of the MCAN interrupts in register 0x0824.

    You are welcome to only use register 0x1050 if you would like, because it is the only register that can clear any set interrupt bits.  However, if you are polling for interrupt registers and SPI efficiency is a concern, then reading both 0x0820 and 0x0824 in a single read transaction is more efficient than two separate reads to registers 0x0820 and 0x1050.

    Regards,

    Jonathan