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Original question:

SN65DP159: Random Screen Blackouts in IDLE State

SN65DP159: SN65DP159RSBT

Malsekar Karthik Krishna
Prodigy 130 points
Part Number: SN65DP159

Tool/software:

Hi Team,

I am using SN65DP159RSBT in retimer mode for my HDMI 2.0 Tx application
Here, I am facing an EDID issue where the source is unable to read the EDID correctly and then proceeds to return an assumed value
This happens only when the monitor goes to sleep mode.
But when the monitor is not in standby/sleep mode for about 5-10 secs (where it displays no signal) and then we the source attempts to read an EDID, it will provide the details correctly
1. Is there something settings that should keep the monitor awake so as to read it whenever required
2. Should the retimer be responsible to keep the monitor awake?
3. Can it be possible that Monitor should send the EDID to source even when it is in Standby/sleep mode, but the retimer is not able to?
4. What is the purpose of DDC clock stretching here? Can i implement this? As i am confused due to the note on voltage levels that can be different on source and sink side (source is 3V3 and sink is 5V)

Based on the previous queries, we have one more setup (same setup and configuration) on which there is no toggling on the DDC lines at the sink side, we tried to give reflow multiple times but there is no improvement. Seems like the DDC Block is inactive.

For both the setup, OE pin is been provided with 2ms delay through an RC circuit since the 1V2 VDD will be arriving at 1.4ms while the 3V3 will be at instance 0ms.
Attached is the schematics, please let me know if any other details is required.

Regards,
M Karthik

  • 0
    TI__Guru**** 178516 points

    M Karthik

    What is being connected at the DP159 input? Is it a DP++ source and are you AC coupling the DP159 input?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 130 points

    Hi David,

    We are using a 9EG MPSoC SBC as a source, and yes, the source is AC coupled to the input of DP159

    Regards,
    M Karthik

  • 0 in reply to Malsekar Karthik Krishna
    TI__Guru**** 178516 points

    M Karthik

    The only time the DP159 DDC will disable its DDC is when it is in Power Down Mode. Below table shows the conditions the DP159 will be in the Power Down mode.

    But in normal operation, DDC should be enabled. 

    The DDC clock stretching is enabled by default and there is no way to disable it. But this is separate from the 5V to 3.3V level shifting. The DDC clock stretching is a mechanism where DP159 can temporarily hold the Serial Clock (SCL) line low, delaying the source device's clock signal and thus slowing down or pausing communication. It is important that the source supports DDC clock stretching. If the source does not support clock stretching, then you will have to use an external DDC level shifter and put DP159 into the DDC snooping mode. 

    I believe the monitor will go into the sleep mode when there is no input signal, but please verify this with the monitor vendor. It is also up to the monitor vendor on how to handle the DDC communication when it is in the sleep mode. 

    Looking at the schematic, can you please provide the setting for these strap pins?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 130 points

    Hi David,

    David (ASIC) Liu said:
    I believe the monitor will go into the sleep mode when there is no input signal, but please verify this with the monitor vendor. It is also up to the monitor vendor on how to handle the DDC communication when it is in the sleep mode

    We have tried with multiple displays all resulting in the same EDID assume value when in standby/sleep mode
    Is there anything that can forcefully keep the displays awake, or force the display to wake up when I am willing to read the EDID from my SBC (source)?
    Or any settings is required to be enabled so that my source can read the EDID correctly even when the monitor/displays are in standby/sleep mode?

    David (ASIC) Liu said:
    Looking at the schematic, can you please provide the setting for these strap pins?

    The settings for strap pins are as is in the schematics, mentioned below for your reference

    Regards,
    M Karthik

  • 0 in reply to Malsekar Karthik Krishna
    TI__Guru**** 178516 points

    M Karthik

    We have tried with multiple displays all resulting in the same EDID assume value when in standby/sleep mode
    Is there anything that can forcefully keep the displays awake, or force the display to wake up when I am willing to read the EDID from my SBC (source)?
    Or any settings is required to be enabled so that my source can read the EDID correctly even when the monitor/displays are in standby/sleep mode?

    This question is more for the monitor vendor. But does the monitor go into standby/sleep mode when there is no output out of the DP159? 

    Looking at the strap configuration, I would leave the SLEW, Pre_SEL, and EQ_SEL all floating as the initial configuration.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 130 points

    Hi David

    Will change the strap settings and update it to you.

    David (ASIC) Liu said:
    But does the monitor go into standby/sleep mode when there is no output out of the DP159? 

    1. While booting the SBC, we are not channeling any output, we will only be reading the EDID, once that is successful, we will move forward with test image pattern and GPU testing, which have done already and is working well. The monitor/display goes to sleep when the SBC is booting, whereas the voltages are OE are high well enough by this time.

    David (ASIC) Liu said:
    Looking at the strap configuration, I would leave the SLEW, Pre_SEL, and EQ_SEL all floating as the initial configuration.

    2. Will these strap settings hinder in the already carried out GPU tests results, as there were no quality issues.

    3. We have one more setup where the EDID will not be read even when the monitor/display is awake, previously it had HPD issues which got resolved by multiple reflow and touchups, but when we probe EDID lines at the sink side, they do not toggle.

    Meanwhile, we are in contact with the display vendors and also share the update to you on this.

    Regards,
    M Karthik

  • 0 in reply to Malsekar Karthik Krishna
    TI__Guru**** 178516 points

    M Karthik

    With EQ_SEL set to high and 14dB equalization, the signal may be get over-equalized and signal quality will be poor. I would expect with the change in the strap pin setting, you will see better signal quality. 

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 130 points

    Hi David,

    Can you please help us on the other queries too

    Malsekar Karthik Krishna said:
    1. While booting the SBC, we are not channeling any output, we will only be reading the EDID, once that is successful, we will move forward with test image pattern and GPU testing, which have done already and is working well. The monitor/display goes to sleep when the SBC is booting, whereas the voltages are OE are high well enough by this time.
    David (ASIC) Liu said:
    But does the monitor go into standby/sleep mode when there is no output out of the DP159?

    Malsekar Karthik Krishna said:
    3. We have one more setup where the EDID will not be read even when the monitor/display is awake, previously it had HPD issues which got resolved by multiple reflow and touchups, but when we probe EDID lines at the sink side, they do not toggle.

    Regards,
    M Karthik

  • 0 in reply to Malsekar Karthik Krishna
    TI__Guru**** 178516 points

    M Karthik

    The monitor/display EDID is not controlled by DP159. Please see below table for the DP159 control logic and mode of operation.

    When both OE and HPD_SNK are high in pin strap mode, then the DP159 DDC buffer is active and will pass the monitor/display EDID info to the source.

    Thanks

    David