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DS90UB928Q-Q1: Any register to indicate the empty package?

Daniel Wang (auto)
Expert 4850 points

Part Number: DS90UB928Q-Q1

Tool/software:

Hello team,

Debugging the 928, we found that when there was no video stream from the Ser to 928 (for example, the test pattern script was turned off). The device can lock and work normally, we want to know if there is any register to indicate the empty package.

Thanks

Regards,

Daniel

  • 0
    TI__Mastermind 27865 points

    Hi Daniel,

    Who is the tier 1 and OEM? And what is the partner serializer?

    Are you sure that LOCK is HIGH when the video is not being sent from the upstream serializer? By default, FPD-Link III deserializers require a video stream in order to establish LOCK.

    Best,

    Nikolas

  • 0
    Prodigy 40 points

    Hello Nikolas 

    I am  engineer from Conti Wuhu, 

    1. We had tested on three types of Serializers:UH983，HH983，UH949, when the lock pin is high, but there is no input video, the deser 928 always outputs clock signal but without data signals. We want to know if this can be configed by a register whether output a clock or not when there is no input video stream.
    2. Where is the registers of VSYNC, HSYNC, DE or error flag status register(we can't find status regs in ds90ub928q-q1.pdf), so we can judge whether a video stream is coming or not?

    Look forward to your feedback , Thanks !!

  • 0 in reply to Ye Huaying
    TI__Mastermind 27865 points

    Hi Ye,

    Ye Huaying said:
    We had tested on three types of Serializers:UH983，HH983，UH949, when the lock pin is high, but there is no input video, the deser 928 always outputs clock signal but without data signals. We want to know if this can be configed by a register whether output a clock or not when there is no input video stream.

    I'd like to discuss the FPD-Link IV devices on the internal forum. Please work with Daniel to have your questions migrated there.

    Regarding UH949, by default the FPD-Link III deserializers require a video stream in order to establish LOCK. This is controlled on the deserializer side via register 0x34[6]. See below from the UB928 data sheet:

    Please double check that no active video is being sent upstream - if the default register settings are being utilized then LOCK should not be established on the downstream deserializer. If LOCK is established and 0x34[6] = 0, then some form of video is being received by the UB928.

    Ye Huaying said:
    Where is the registers of VSYNC, HSYNC, DE or error flag status register(we can't find status regs in ds90ub928q-q1.pdf), so we can judge whether a video stream is coming or not?

    There are no such registers on the UB928, unfortunately.

    Best,

    Nikolas

  • 0 in reply to Nikolas Antonucci
    Prodigy 40 points

    Hello Nikolas

    Thanks for your feedback !

    This register is set to 0 (0x34[6] = 0,), does it mean that the lock cannot be checked in real time?

    By the way ,I cannot see the screenshot in the datasheet we have , Could you share the version you have ? 

  • 0 in reply to Ye Huaying
    TI__Mastermind 27865 points

    Hi Ye,

    Ye Huaying said:
    This register is set to 0 (0x34[6] = 0,), does it mean that the lock cannot be checked in real time?

    No - if 0x34[6] = 0, then LOCK is only asserted when receiving active video. If LOCK is HIGH with 0x34[6] = 0, then it means some form of active video is being sent from upstream. 

    Ye Huaying said:
    By the way ,I cannot see the screenshot in the datasheet we have , Could you share the version you have ? 

    The version of the data sheet I have is the same as the one on ti.com - SNLS417C.

    Best,

    Nikolas