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TCAN4550: Clarification on Rise/Fall Time vs. Bit Width Requirements

Stav Lahat
Prodigy 10 points
Part Number: TCAN4550

Tool/software:

Hi Team,

I have a question regarding the rise and fall time specifications in the datasheet.

I'm operating at a frequency of 2 MHz and observing a fall time of approximately 60 ns, which corresponds to 12% of the bit width. According to our requirements, the fall time should not exceed 10% of the bit width to ensure signal integrity.

However, the datasheet specifies a maximum fall time of 75 ns, even though the maximum supported frequency is listed as 8 MHz. This seems to imply a fall time that would exceed 10% of the bit width at higher frequencies.

Could you please clarify how this aligns with your design requirements or provide guidance on how to interpret these values?

Thank you in advance for your support.

Best regards,
Stav Lahat

  • 0
    TI__Mastermind 33030 points

    Hi Stav,

    I assume you are referring to the rise/fall times of the CANH and CANL signals.  If so, these will vary with bus loading.  Recessive-to-Dominant edges are actively driven, and Dominant-to-Recessive edges are passively pulled back to the recessive level through the termination and bus biasing resistors located in every transceiver.

    The TCAN4550 meets the requirements in the ISO 11898-1:2015 and ISO 11898-2:2016 Standards.  There is not a direct rise of fall time specification for CANH and CANL and instead the transmitter and receiver bit timing behavior is monitored based on the bit width of the TXD and RXD signals under defined load conditions.

    I don't know how your requirements align with the ISO 11898-1/2 standards.  The internal TXD and RXD signals between the controller and transceiver can be accessed through the GPIO1 and GPO2 pins by placing the device into one of the Test Modes and will allow you to run tests according to the ISO 11898 standards.

    Regards,

    Jonathan