SN65DSI86: The screen suddenly went black during use, but there was still backlight

Hi Haibin,

For this case, I recommend performing the following procedure:

• Register dump (all registers readback value) during normal operation 
• Register dump during black screen with backlight still normal

There are several diagnostic registers that are available in the device, which could help pinpoint which function (input/output protocol) is having issues during runtime.

A direct comparison of these two logs would inform which configurations changed easily and what to focus on from there.

Here's an example script:

import time

devReadAddress = 0x2C

pages, registers = (1, 255)
arr = [[0]*registers]*pages

dateTime = time.strftime("%Y%m%d-%H%M%S")
csv_name = 'PageDump' + str(devReadAddress) +'_'+  dateTime  + '.csv'
f1=open(csv_name, 'w+')

for x in range(-1,registers+1,1):
	if x==-1:
		f1.write(str("")+",")
	else:
		val = hex(x)
		#print val,
		f1.write(str(val)+",")
#print ""
f1.write("\r")

for x in range(-1,registers+1,1):
	if x==-1:
		f1.write("MainPage"+",")
	else:
		val = hex(board.ReadI2C(devReadAddress,x))
		#print val,
		f1.write(str(val)+",")
print "Main Page Done"
#print ""
f1.write("\r")

for y in range(1,pages+1,1):
	board.WriteI2C(devReadAddress,0x40,y*4+3)
	board.WriteI2C(devReadAddress,0x41,0x00)
	for x in range(-1,registers+1,1):
		if x==-1:
			#print 'Page'+str(y),
			f1.write("Page"+str(y)+",")
		else:
			val=board.ReadI2C(devReadAddress,0x42,1)
			#print hex(val),
			f1.write(str(hex(val)) + ",")
	#print ""
	print 'Page',y,' Complete'
	f1.write("\r")
f1.flush()
f1.close()
print "Complete"

Could you also provide any additional conditions during the testing, if any?

Thanks,

Miguel

Black.csvOK.csv

The attachment OK.csv shows the dump information when displayed normally, while black.csv shows the dump information when the screen is black.

sn65dsi86 initial code:

int sn65dsi86_init(void)
{
	sn65dsi86_write(0x09, 0x00); // SW Reset
	sn65dsi86_write(0x0A, 0x09); // DACP/N CLOCK FREQ 460.8MHz
	sn65dsi86_write(0x0D, 0x00); // PLL DISABLE
	sn65dsi86_write(0x10, 0x26); // Single channel DSI receiver A, DSIA 4Lanes
	sn65dsi86_write(0x11, 0x00); // CHA/B DSI DATA/CLK EQ
	sn65dsi86_write(0x12, 0x59); // DSIA CLK FREQ 445~450MHz

	sn65dsi86_write(0x5A, 0x05); // enhanced framing and ASSR
	sn65dsi86_write(0x93, 0x20); // 2 DP lanes no SSC
	sn65dsi86_write(0x94, 0x80); // HBR (2.7Gbps)
	sn65dsi86_write(0x5C, 0x01); // HPD DISABLE

	sn65dsi86_write(0x0D, 0x01); // PLL ENABLE
    mdelay(15);

	sn65dsi86_write(0x95, 0x00);
    /* Write DPCD Register 0x0010A in Sink to Enable ASSR */
	sn65dsi86_write(0x64, 0x01);
	sn65dsi86_write(0x74, 0x00, 0x01, 0x0A); // AUX_ADDR: 0x00010A
	sn65dsi86_write(0x77, 0x01); // AUX_LENGTH: 1
	sn65dsi86_write(0x78, 0x81); // AUX_CMD: 0x8(Native Aux Write), SEND:0x1
	mdelay(10);

    sn65dsi86_write(0x96, 0x0A); // 0x01: Normal TRAIN, 0x0A: Semi-Auto TRAIN
	mdelay(20);

    /* W = 1920(0x0780) */
	sn65dsi86_write(0x20, 0x80, 0x07);
    /* H = 1080(0x0438) */
	sn65dsi86_write(0x24, 0x38, 0x04);
    /* HS = 44(0x002C) */
	sn65dsi86_write(0x2C, 0x2C, 0x00);
    /* VS = 5 , CHA_VSYNC_POLARITY active low Pulse */
	sn65dsi86_write(0x30, 0x05, 0x00);
    /* HBP = 148 */
	sn65dsi86_write(0x34, 0x94);
    /* VBP = 36 */
	sn65dsi86_write(0x36, 0x24);
    /* HFP = 88 */
	sn65dsi86_write(0x38, 0x58);
    /* VFP = 4 */
	sn65dsi86_write(0x3A, 0x04);
    sn65dsi86_write(0x5A, 0x0D); // enhanced framing, ASSR, and Vstream enable

    mdelay(10);
    return 0;
}

Haibin,

Thanks for providing this detailed information.

From the register logs I can only see one difference between these DP registers, the MDIV is different for the CSR:

0x40 = 0xCD (205d) --> 0x40 = 0xD2 (210)

This is seen from the DisplayPort perspective.

I can only imagine this runtime issue occurs after some clock delay or frequency shifting since the MDIV value changes, is there any diagnostics from the source side or sink display that indicates any timings are changed?

Can you try setting this MDIV to the normal log value (0xCD) and see if the screen will blank after the given duration?

Best,

Miguel

Thanks for your reply！

I reported this phenomenon to the screen factory, and they measured that the eDP main link frequency was 2.62G, which does not comply with VESA specifications. Then I adjusted the MIPI clock (HS/HBP/HFP/VS/VBP/VFP, etc.), and changed the 0x12 register from 0x59 to 0x5A. The measured eDP main link frequency was 2.64G, and the black screen phenomenon did not reappear, but still did not meet the VESA specification of 2.7G, which may still pose a risk. The 0x94 register of sn65dsi86 has been confirmed to be set to 2.7G (corresponding to a register value of 0x80). How can I ensure that the output main link frequency of sn65dsi86 is 2.7G?

The modified initialization code is as follows:

int sn65dsi86_init(void)
{
	sn65dsi86_write(0x09, 0x00); // SW Reset
	sn65dsi86_write(0x0A, 0x09); // DACP/N CLOCK FREQ 460.8MHz
	sn65dsi86_write(0x0D, 0x00); // PLL DISABLE
	sn65dsi86_write(0x10, 0x26); // Single channel DSI receiver A, DSIA 4Lanes
	sn65dsi86_write(0x11, 0x00); // CHA/B DSI DATA/CLK EQ
	sn65dsi86_write(0x12, 0x5A); // DSIA CLK FREQ 450~455MHz

	sn65dsi86_write(0x5A, 0x05); // enhanced framing and ASSR
	sn65dsi86_write(0x93, 0x20); // 2 DP lanes no SSC
	sn65dsi86_write(0x94, 0x80); // HBR (2.7Gbps)
	sn65dsi86_write(0x5C, 0x01); // HPD DISABLE

    /* W = 1920(0x0780) */
	sn65dsi86_write(0x20, 0x80, 0x07);
    /* H = 1080(0x0438) */
	sn65dsi86_write(0x24, 0x38, 0x04);
    /* HS = 44(0x002C) */
	sn65dsi86_write(0x2C, 0x2C, 0x00);
    /* VS = 8 , CHA_VSYNC_POLARITY active low Pulse */
	sn65dsi86_write(0x30, 0x08, 0x00);
    /* HBP = 148 */
	sn65dsi86_write(0x34, 0x94);
    /* VBP = 27 */
	sn65dsi86_write(0x36, 0x1b);
    /* HFP = 88 */
	sn65dsi86_write(0x38, 0x58);
    /* VFP = 20 */
	sn65dsi86_write(0x3A, 0x14);

	sn65dsi86_write(0x0D, 0x01); // PLL ENABLE
    sunxi_lcd_delay_ms(20);

	sn65dsi86_write(0x95, 0x00);
    /* Write DPCD Register 0x0010A in Sink to Enable ASSR */
	sn65dsi86_write(0x64, 0x01);
	sn65dsi86_write(0x74, 0x00, 0x01, 0x0A); // AUX_ADDR: 0x00010A
	sn65dsi86_write(0x77, 0x01); // AUX_LENGTH: 1
	sn65dsi86_write(0x78, 0x81); // AUX_CMD: 0x8(Native Aux Write), SEND:0x1
	sunxi_lcd_delay_ms(40);

    sn65dsi86_write(0x96, 0x0A); // 0x01: Normal TRAIN, 0x0A: Semi-Auto TRAIN
	sunxi_lcd_delay_ms(20);

    sn65dsi86_write(0x5A, 0x0D); // enhanced framing, ASSR, and Vstream enable

    return 0;
}