DS90UB953-Q1: MIPI signal error issue

Hello Vayne,

Just to clarify:

1) Is the customer using any EVMs? Or is it fully custom hardware?

2) Is the video being outputted by a camera sensor (Imager -> SER -> DES -> SoC)?

3) Has the customer tried enabling the test pattern video generator (PATGEN) on the serializer, to see if the same MIPI error is detected at the SoC?

4) Are there any errors being detected at the RX Port diagnostics registes in the 954 device?

Set 954 reg 0x4CC = 0x01 (Selects RX Port 0)

Read 954 reg 0x4D,  0x4E, 0x55, 0x56, 0x7A, 0x7B

Note that some of these registers are error flags that may be accidentally set during power-up. Read these diagnostics errors several times and see if any errors are presistently being detected.

Best,

Justin Phan

Hi Justin,

The register values of 954 read in case of abnormal situations are as follows

0x4D:0x17; 0x4E:0x24; 0x55:0x01; 0x56:0x1E; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x04; 0x55:0x00; 0x56:0x00; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x04; 0x55:0x00; 0x56:0x78; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x04; 0x55:0x00; 0x56:0x16; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x24; 0x55:0x00; 0x56:0x24; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x24; 0x55:0x00; 0x56:0xD5; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x0C; 0x55:0x00; 0x56:0x00; 0x7A:0x02; 0x7B:0x01;
0x4D:0x13; 0x4E:0x24; 0x55:0x00; 0x56:0x02; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x04; 0x55:0x00; 0x56:0x4F; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x0C; 0x55:0x00; 0x56:0x02; 0x7A:0x02; 0x7B:0x01;
0x4D:0x13; 0x4E:0x65; 0x55:0x00; 0x56:0x0A; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x04; 0x55:0x00; 0x56:0x01; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x24; 0x55:0x00; 0x56:0x16; 0x7A:0x00; 0x7B:0x00;

Customer ran the four routes a hundred times, This is taken from the thirteen times where there were errors.

Hello Vayne,

Out of a hundred times run, it seems that they meet errors at around 13 times.

1. On the good runs, do they get the expected results shown above? Or are they also getting similar error flags?
2. Is any hardware being changed before each run? Or are you just power-cycling the system, but the system starts getting failures on some runs?

Best,

Justin Phan

Hi Justin,

On the good runs,many of the values read from the 954 register are also 0.

Testing 100 times only involves a power on and restart cycle, without changing the hardware

0x4D:0x13; 0x4E:0x45; 0x55:0x00; 0x56:0x04; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x45; 0x55:0x00; 0x56:0x24; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x65; 0x55:0x00; 0x56:0x01; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x45; 0x55:0x00; 0x56:0x00; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x45; 0x55:0x00; 0x56:0x3D; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x65; 0x55:0x00; 0x56:0x16; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x65; 0x55:0x00; 0x56:0x0B; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x65; 0x55:0x00; 0x56:0x7E; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x65; 0x55:0x00; 0x56:0x1B; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x45; 0x55:0x00; 0x56:0x01; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x65; 0x55:0x00; 0x56:0x8B; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x45; 0x55:0x00; 0x56:0x00; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x45; 0x55:0x00; 0x56:0x77; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x45; 0x55:0x00; 0x56:0x02; 0x7A:0x00; 0x7B:0x00;
0x4D:0x13; 0x4E:0x65; 0x55:0x00; 0x56:0xF3; 0x7A:0x00; 0x7B:0x00;

Hello Vayne,

If power cycling is sometimes causing these issues, is it possible that the power-up sequence defined in the 954 or 953 is being violated on specific power-up cycles? Can you verify that the noise on the 954 and 953 IC pins is within spec?

When the system has stable LOCK, can the customer run the MAP script, to evaluate the margin on the link?

This can be done through the 954 ALP tab. Or by running the MAP script that is included in the installation of ALP, under the PreDefined Scripts folder.

And just to clarify, for each test, is the customer generating video from an external image sensor and feeding it through our SerDes devices? Is it possible to run this test with the imager disabled and to have the serializer generate a test video pattern instead?

Best,

Justin Phan

Hi Justin,

Thank you for your guidance. My customer has probably identified the issue. They are currently investigating SOC timing and would like to ask if there are any register settings in the serializer or deserializer that can adjust the order of MIPI LANE?

Hello Vayne,

Could you clarify what you mean by "order of MIPI LANE"?

Are you asking if it is possible to program specific MIPI lanes to be either D0, D1, D2, D3, or CLK? If so, then unfortunately, we cannot do that. We can only disable/enable a set of MIPI data lanes, but we cannot reprogram the functionality of each MIPI pin.

Best,

Justin Phan

Hi Justin,

What I want to express is the sequence of MIPI lane.This is the explanation section of the customer's SOC regarding the mipi timing sequence

Hello Vayne,

The 954 and 953 are both compliant to MIPI D-PHY v1.2 and can operate within the timing specifications defined under the MIPI standard. The MIPI timing for each device is defined in the datasheet as well.

Customers can follow the general MIPI D-PHY data rate configuration instruction settings defined in the datasheet, to get their desired MIPI rate while also being compliant to the timings in the MIPI standard. The only exception is for the 400Mbps per lane rate, which requires an additional configuration step to meet the timing defined in the MIPI standards.

What is the data rate that the customer is using on the 954 MIPI transmitter port?

If it is 400Mbps per lane, then make sure they have run this script. If it anything except 400Mbps per lane, then the customer does not need to run any special script to make the 954 device meet the MIPI compliant timings.

Best,

Justin Phan