DP83843: potential issue with over 50ppm at Clock Interface X1

Hi Oka-san, 

We have limited design support for this part, so we are unsure of possible ramifications of using clock over the recommended ppm. However, please note that the ppm from the input clock will be outputted to the output clock and affect other devices that uses the output clock from the PHY. 

Best,
J

Hi J,

May I know what kind of issue would be expected to other devices that uses the output clock from the PHY? Just expectation or opinion is also helpful for customer.

Hi Oka-san, 

There will be increased jitter so the clock may not be as accurate as required by other devices. 
In addition, because this part is so old, we have limited design support. If you could ask the customer to use our newer devices like DP83822, that would be great. 
Best,
J

How about using only 10BASE-T (not 100BASE-T) ? Is there any additional information? Customer want to know anything. Just expectation or opinion is also helpful for customer.

Hi Oka-san, 

The same applies for 10Base-T. We expect the jitter from the input clock to carry over to the MII/RMII clock signal since it uses recovered clock. The jitter may impact the MII communication. 

Best,
J