TUSB1210: The outpu delay of NXT and DIR

chunli Liang

Part Number: TUSB1210

Tool/software:

I am currently using the TUSB1210BRHBR in my design.

I have measured the output delay of NXT and DIR, and both are consistently below 1.2 ns.

Here are the details of my testing environment:

‌FPGA : XCAU7P-L1SBVC484I

‌Oscilloscope‌: 3-Series MDO Mixed-Domain

‌Probe‌: TPP1000

Clock is Output Mode.

The datasheet for the TUSB1210BRHBR specifies an output delay range of 1.2 ns to 5.5 ns.

According to the ULPI 1.1 specification, the delay should be less than 9.0 ns.

Are there any potential risks or concerns with operating outside the datasheet specifications, even though the ULPI specification is met?

Thanks and Best Regards

Chunli Liang

0 Vishesh Pithadiya 2 months ago

Hi,

The expert on this part is currently OoO, they will be back tomorrow. I will make sure they get to this tomorrow.

Thanks for your patience.

0 Brian Zhou 2 months ago in reply to Vishesh Pithadiya

HI Chunli:

What FPGA used for your application?

Best

Brian

0 chunli Liang 2 months ago in reply to Brian Zhou

Hi Brian

I have two project.

The one will use TUSB1210 with Artix UltraScale+ FPGA.

The other will use TUSB1210 with the PS' USB controller of Zynq UltraScale+ MPSoC FPGA.

Thanks and Best Regards

Chunli Liang

0 Brian Zhou 2 months ago in reply to chunli Liang

Hi Chunli:

There is timing issue between TUSb1210 and Zynq -7000 FPGA, but it's ok for other SOC/FPGA.

Best

Brian

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