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XIO2001: Regarding the XIO2001IPNP malfunction

Kyohei
Expert 1440 points
Part Number: XIO2001

Tool/software:

Hi team,

Regarding to Errata 1 (Using Serial Interrupts may result in multiple MSI messages being sent.),

is it possibgle that the XIO2001 sends corrupted TLP from PCIe Port side when high traffic

situation and Max Payload size is 256 Byte (larder then 200Byte)?

 

The XIO2001 is mounted on our developing board. At the PCIe side, it is connected to PCIe Root Port.  

At the PCI Local Bus side, there are 3 PCI slots and PCI 1GbE LAN Cards are set.

 

When we inject LAN traffic to those 3 PCI LAN cards for about 10 hours, the PCIe Root Port detects

a Malformed TLP.  A header log which is recorded at the PCIe Root Port is the following.

 

HEADER LOG0: 0xA532_1E68

HEADER LOG1: 0xA002_CEA5

HEADER LOG2: 0x0000_0000

HEADER LOG3: 0x0000_0000

*We think that this TLP is corrucpted (TLP Type A5h is not defined in PCIe Specification) .

 

But when we set Max Payload Size at the PCIe side to 128Byte and inject same traffic,

we had not seen Malformed TLP for over 72 hours.  

 

[PCI Configuration register settings]

At the PCIe Port of the XIO2001, the INTx emulation interrup is uesed.

- Interrupt Disable bit (Command Register) is 0b.

- MSI Enable bit (Message Control Register) is 0b.

Best regards,

Kyohei

  • 0
    TI__Mastermind 38885 points

    Hi,

    The expert on this part is currently OoO. They will return tomorrow. Thanks for your patience.

  • 0 in reply to Vishesh Pithadiya
    TI__Guru*** 145550 points

    HI Kyohei:

      It could be Max Payload size(MPS) setting is different in Device control register of different devices.  128 Byte  is the MPS value every device can accept.

    Best

    Brian

  • 0 in reply to Brian Zhou
    Expert 1440 points

    Hi Brain,

    Thank you for your support.

    It has been confirmed that the issue improves when the Max Payload Size (MPS) is set to 128 bytes on both the PCIe Root Port side and the XIO2001 PCIe Port side.
    Does this correspond to Errata Item 1?
    Also, we understand that Errata Item 1 refers to a fault where interrupt handling may be invoked multiple times.
    Is there a possibility that this could lead to corrupted TLPs as a side effect?

    Best regards,

    Kyohei

  • 0 in reply to Kyohei
    TI__Guru*** 145550 points

    Hi Kyohei:

       Errata 1 issue is timing dependent. Your issue was due to mismatch between  MPS setting in Device control register of different devices which caused  Malformed TLP.

    Regards

    brian

  • 0 in reply to Brian Zhou
    Expert 1440 points

    Hi Brian,

    Thank you for your support.

    After confirming with the customer, they stated:

    "In the environment where this issue occurred, both the PCIe root port side and the PCIe port side of the XIO2001 had the MPS setting configured to 256 bytes. Therefore, this is not a case of a Malformed TLP caused by mismatched MPS settings."

    Given this, is it appropriate to consider that this falls under Errata Item 1?

    Best regards,

    Kyohei

  • +1 in reply to Kyohei
    TI__Guru*** 145550 points

    Hi Kyohei:

      Since it's not MPS setting issue, it  can be considered under Errata item 1.

    Best

    Brian