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TDES960: Schematic Review Request for Custom Board Integrating Arducam V3Link Adapter with AM68A .

Part Number: TDES960
Other Parts Discussed in Thread: AM68A, TSER953,

Tool/software:

Hello TI Community,

I am developing a custom board based on the AM68A reference design. The original reference supports only two camera inputs, but my application requires interfacing three cameras. To enable this, I used Arducam V3Link D-CH Adapter Boards, which use TI’s FPD-Link III SerDes solution ( TDES960RTDR deserializer).

Configuration Tried:

  • When I connected 3 cameras to a single Arducam V3Link adapter, I was unable to achieve high-resolution video streams reliably.

  • When I reconfigured to connect 2 cameras on one adapter and the 3rd on a separate adapter, the system worked properly in high-resolution mode.

Based on this observation, I decided to integrate the Arducam V3Link adapter circuits directly into my custom board. I have created a schematic for this integration using the TDES960RTDR and multiple DS90UB953 serializers.

Request:

Could someone from the TI team or the community please review my schematic for correctness, signal integrity, power requirements, and any potential configuration issues—especially regarding:

  • Multi-camera synchronization

  • CSI/DSI routing to AM68A

    PDB, GPIO, and I2C handling for serializer/deserializer

  • FPD-Link III layout considerations (coax/STP routing)

I have attached the schematic PDF for your review.

Arducam.pdf

  • Hello,

    Thank you for reaching out. Please note that the TDES960 is part of the V3Link portfolio, and the DS90UB953 is part of the FPD-Link portfolio. The portfolios are not inter-compatible, and the TDES960 and DS90UB953 should not be paired together. The correct serializer for the TDES960 is the TSER953. However, the TSER953 has the same pin out as the DS90UB953, so the peripheral components do not need to be changed, only the part number of the serializer.

    With that being said a review of the TDES960 can still be completed, just note that only the portion directly related to the TDES960 can be reviewed. For a review of the power tree, please create a different ticket for the power team (the ticket will be assigned to the appropriate team based on the chosen part number). To confirm, the desired system is two boards each with a TDES960. The first board will connect to 2 cameras, and the second board will connect to one camera. Is this correct? Will each board have a separate AM68A SoC? The review will take 3-4 days, but please see feedback on the configuration questions below:

     

    • Multi-camera synchronization
      • To synchronize cameras, a frame sync signal can be used. A frame sync signal is a signal that is generated by the system (typically the deserializer or SoC), which is sent to the cameras. The cameras will use the received signal to output data. Since each camera is outputting data using the same sync signal, all the output data will be synchronized. The deserializer will send the signal to each partner serializer over the back channel, and each serializer will then send the signal to the respective camera. The frame sync signal can either be generated by the deserializer or sent to the deserializer from the SoC via a GPIO pin. For more details on frame sync, please see section 7.4.24 of the TDES960 data sheet.
    • CSI/DSI routing to AM68A
      • The TDES960 only supports CSI data, DSI is not supported. When routing CSI traces, please follow the guidelines in section 8.5.1.3 of the TDES960 data sheet.
    • PDB, GPIO, and I2C handling for serializer/deserializer
      • Each serializer and deserializer has a specific power sequence that must be followed for proper operation. The power sequence includes the PDB signal, all power signals, and sometimes GPIOs. The power sequence for each device can be found in the device’s respective data sheet in the “Typical Application” section.
      • Other than GPIO requirements in the power sequencing, there are no specific requirements related to the GPIO pins. GPIO pins can be configured to operate as inputs or outputs, and can even be left floating if unused.
      • Partner deserializers and serializers can communicate using I2C automatically over the back channel and forward channel. The only caveat to this is that the serializer and deserializer must have stable lock. The I2C addresses of the devices are set during power up based on the voltage seen on the IDX pin.
    • FPD-Link III layout considerations (coax/STP routing)
      • When routing FPD-Link traces, please follow the guidelines in section 8.5.1.2 of the TDES960 data sheet. Coax and STP configurations do require different hardware configurations. Ensure that the traces and physical termination of the RIN+/- and DOUT+/- traces align with the desired configuration.

     

  • Hello,

    Please find feedback on the TDES960 components below. This feedback is applicable to both TDES960s in the schematic.

    • Recommend using capacitors with a 50V rating on the RIN+/- pins
    • Recommend disabling the unused RIN ports by setting the RX_PORT_CTL control bit to 0 for each respective unused port
    • Recommend verifying that 4.7k pull up resistors are suitable for the system’s I2C bus
    • IDX pin is currently programmed to select I2C address of 0x30/0x60 (7bit/8bit). If this is the desired address disregard
    • Mode pin is currently programmed to select CSI-2 Non-Synchronous mode. If this is the desired mode, disregard
    • Not clear if R1 is meant to be a placeholder for a future ferrite beads, but VDDIO only requires the capacitors not a ferrite bead or other components
    • Verify that 25MHz clock is suitable for the system. REFCLK impacts the CSI output speed and the forward channel speed. Also verify that the 25MHz signal can meet the requirement in section 7.4.4 of the device data sheet
    • For CMLOUT operation the positive and negative terminals should have 100 ohm termination resistor.
    • Double check that the board follows the power sequencing requirements (section 8.4.2 of device data sheet)
    • Verify that ferrite beads meet a DCR <= 25 25 mOhm and impedance >= 120 Ohm @ 100MHz
    • PoC network looks similar to the network in the data sheet, but it is recommended to validate/test the network to ensure that will perform as expected.
    • Note that both TDES960 parts are being configured with the same I2C address. If the two deserializers are connected on the same I2C bus this could cause a communication conflict.
  • In the review feedback for our AM68A-based custom board integrating two TDES960 deserializers (each connected to an Arducam V3Link adapter), the following was noted:

    “Both TDES960 parts are being configured with the same I²C address. If the two deserializers are connected on the same I²C bus this could cause a communication conflict.”

    In our design, the AM68A has two independent CSI interfaces, each with its own I²C connection routed through separate I²C mux channels. Each TDES960 is connected to a different mux address

    Since these I²C lines are isolated via separate mux channels, is it still necessary to assign different I²C addresses to the two TDES960 devices? Or is it acceptable to keep both at the default address without causing conflicts?

  • Hello,

    If the devices are on entirely separate I2C buses, this is okay. A conflict will only occur if both devices are able to receive the same I2C transactions, as both devices will attempt to respond to the same address causing a conflict.