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DP83867IRPAP-EVM: Support Needed for DP83867IRPAP – LED_2 Link Status Issue

Pavithran Gunasekaran
Prodigy 45 points
Part Number: DP83867IRPAP-EVM
Other Parts Discussed in Thread: DP83865

Tool/software:

Dear TI Support Team,

We have migrated from the DP83865 to the DP83867IRPAP due to EOL. The PHY is configured in GMII mode and PHY address is set to 0x01.

In our previous design (with DP83865), we used an LED signal to indicate Ethernet link status, which was connected to our FPGA. When the cable was removed, the system detected it and showed “waiting for Ethernet ready.”

In our new design:

  • We connected LED_2 (pin 61) of DP83867 to the FPGA (named glink_status).

  • LED_2 is not used as a strap.

  • The signal always stays HIGH, even when the Ethernet cable is removed.

  • There is no issue with scan or data communication – we are able to send and receive packets successfully.We would like your help on the following:

  1. How can we configure LED_2 to indicate link status correctly?

  2. Is there any recommended strap or register setting to fix this?

  3. Is a pull-down or pull-up resistor required on LED_2 if not used as a strap?

  4. Any reference design or application note that shows this setup?

Please guide us on how to make LED_2 work reliably for link detection.

 Existing Design 





current Design schematic

Thanks & Regards,
Pavithran Gunasekaran

  • 0
    TI__Genius 12461 points

    Hi Pavithran, 

    LED2 pin auto-detects the polarity at the power up. LED_2 pin also is set to show TX/RX activity so if there is link and packet transmission the LED will be ON. 
    To indicate link status, you will have to change the register setting below:



    Below is the strapping recommendation from our datasheet:



    Please let me know. 

    Best,
    J

  • 0 in reply to J
    Prodigy 45 points

    Hi Team ,

    Thanks for the quick response.

    I understand that LED_2 is configured by default to show TX/RX activity. However, our specific requirement is as follows:

    We want LED_2 to reflect the actual link status — i.e., the signal should change state when the Ethernet cable is connected or removed. This is necessary so that our FPGA logic can detect cable presence and display "waiting for Ethernet ready" accordingly.

    Could you please confirm:

    1. Is this behavior achievable by changing only hardware strapping (e.g., resistors)?

    2. Or is a register configuration (via MDIO or boot mode override) also needed?

    3. If register change is required, which specific register and value should be used to set LED_2 to reflect link status only?

    Any recommendations or reference configurations would be very helpful.

    Thanks again for your support.

    Best regards,
    Pavithran Gunasekaran

  • 0 in reply to Pavithran Gunasekaran
    TI__Genius 12461 points

    Hi,

    1. The described behavior will not be achievable via hardware strapping.

    2. Register modification via MDIO is required. Please refer to the register screenshot above.

    3. Please refer to the screenshot above.

    Best,

    J