About the SN65LVDS100 differential translator/repeater chip.
The datasheet does not specify the maximum capacitance that the outputs of the chip can drive.
Do you have a number for the maximum cap load that the chip can drive?
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About the SN65LVDS100 differential translator/repeater chip.
The datasheet does not specify the maximum capacitance that the outputs of the chip can drive.
Do you have a number for the maximum cap load that the chip can drive?
It depends on the operation speed and jitter that the system can tolerate. What kind of speed and capacitance loading we are talking about?
Below is customer's reply:
The maximum speed of our LVDS signals isless than 200Mhz. We are interested in finding out the maximum capacitance thatthe SN65LVDS100 can drive. Do you have any graphs or tables that you can send us? What is the primary issue that is seen with capacitive load? I would assume that it is rise/fall time, but you mention jitter in your previous email. Do you have a graph showing jitter vs. capacitance?
You are correct; rise/fall times will be directly impacted by the capacitive load. We don't have any data that shows jitter vs. capacitance but jitter would primarily be a concern at higher speeds.
In order to get you some data regarding maximum load that LVDS100 can drive, we'll either have to simulate or measure it in the lab. We can do that but I need a bit more information about the application:
- Cable or PCB trace length at LVDS100 differntial output
- What's the maximum capacitive load that is expected in this application