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TCAN4550-Q1: SDI Signal Anomaly During Clock Idle

Part Number: TCAN4550-Q1

Tool/software:

I am observing an unusual signal behavior in my waveforms, and I would appreciate some clarification.

In the attached oscilloscope images, you can see that after each word transmission, when the clock momentarily halts before the next word starts, a brief spike appears on the SDI line. This spike lasts for a duration shorter than one bit period.

On the surface, this shouldn't be a problem, as the "bit" is not sampled because SDI is sampled on the rising edge according to the DS. In the second image, you can also see that this spike occurs while the clock is low, so it seems like it wouldn't be sampled/

Could you confirm whether this is expected behavior, or if there might be a potential issue with signal integrity or timing?

Thank you for your assistance!

  • Hello Shachar,

    The SDI signal is an Input to the TCAN4550-Q1 and it is generated by the MCU so the TCAN4550-Q1 is not responsible for causing these extra transitions on the SDI signal.

    My assumption is that the MCU SPI driver is releasing the pin used to drive the SDI signal and allowing it to go Hi-Z after each 8-bit or 1-byte transmission and that there is a pull-up resistance on the line and I can see the SDI signal is also High during the Idle time when CS is also High.

    As long as the SDI signal is at the correct voltage level when the bit is sampled, this shouldn't be an issue.  However, you may also want to look into your MCU SPI driver code to see if you can make any adjustments to keep the SDI pin in a driven state for the complete SPI transaction (while CS is low).

    Regards,

    Jonathan