DP83867IS: DP83867ISRGZT

Hi,

Have you taken a look at the troubleshooting guide: https://www.ti.com/lit/an/snla246c/snla246c.pdf?ts=1754282469726 ?

If so, could you describe your problem with more detail so we can better help you? What is the cable length? How often does the communication not available? Could you verify that the SoC has SGMII connection with the PHY when the communication is not happening?

Best,

J

Subject: Intermittent Link-Down Issue with DP83867ISRGZT PHY over SGMII with Zynq MPSoC

We are currently using the DP83867ISRGZT PHY chip interfaced via SGMII with a Zynq MPSoC in our hardware design.

We are using a 2.5-meter RF45 cable for data communication 

The PHY successfully links up and communicates with the MAC in most power cycles. However, we are observing an intermittent issue where the link occasionally fails.

Issue Summary:

• During repeated board power cycles (approx. 50 iterations), we encounter 2–3 instances where:

  • The PHY does not link up with the MAC.

  • No data communication occurs.

• After the issue appears, performing another power cycle restores normal functionality.

  kindly suggest the solution for sort outing the above issues .

Hi,

Can you verify that the PHY is powered on when the issue happens? If the PHY does power on, could you access the register? If that is not possible, could you try pulling reset low and then high brings the PHY back? If you can access the register, could we see the register dump from 0x00 to 0x1F and 0x25,0x37? If possible, could you share us your schematic also? I will friend request you so you can share via message if that is preferred.

Best,

J

We have powered the PHY and verified that all the power rails are delivering the expected voltage levels.

For your reference, I am attaching the schematic. Kindly review it and let us know if any further action is needed.

Looking forward to your valuable feedback. 

Hi, 

Since the PHY powers up properly, please check the following:
If the PHY does power on, could you access the register? If that is not possible, could you try pulling reset low and then high brings the PHY back? If you can access the register, could we see the register dump from 0x00 to 0x1F and 0x25,0x37?

Below are the comments on the schematic:
1. MDC does not need pull up to VDDIO
2. 
Please ensure that SGMII_D0 and SGMII_D1 strap resistors match so that the loads on SGMII lines are balanced. 
3. 
Looks like LED_0 is strapped to mode 4. This will put the PHY in mirror mode which requires MDI connection to be flipped. Your MDI connection is not flipped so that will cause an issue. Could you put this strap pin in mode 2 (10k pull up and 2.49k pull down) to disable mirror mode?

4. 
We recommend 1uF and 0.1uF per power pin:

5. Is auto-negotiation disabled on purpose?

This has to be in mode 3 to enable auto-negotiation. 

Please let me know. 

Best,

J