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SN65LV1224B deserializer delay time

Patrick Schindzielorz
Genius 10680 points
Other Parts Discussed in Thread: SN65LV1224B

 Hi team,

In the SN65LV1224B datasheet the max. deserializer delay is 1.75 x trcp + 9.7 ns at 66Mhz, which would lead to a delay of 1.75 x 15.15 + 9.7 = 36.21ns. Footnote 1 says "The deserializer delay time for all frequencies does not exceed two serial bit times.", which is 2 x 15.15 = 30.30ns. Which specification is correct?

Also I would like to know the deserializer delay time of 36Mhz operation.

 

Many thanks in advance

Patrick Schindzielorz

  • 0
    TI__Guru 62920 points

    Hi Patrick,

     Unfortunately, this is an older part, and the part designer is no longer with TI.  There is no way to know now why Footnote (1) was included, but I believe that it is erroneous.  You should go with the values calculated from the table (36.21 ns).  The table values should be based off of some measurements performed during device characterization.

     It is not clear from this data what the deserializer delay would be at 36 MHz.  I think the safest route would be to use the formulas for both the 10 MHz and 66 MHz case, and choose whichever value is worse (most likely the higher value).

     If this answer is not sufficient, please let me know.  It may be possible to find some of the original characterization data and try and determine the reason behind the values in the Switching Characteristics table.

     Thank you for pointing out this discrepancy in the datasheet.

    Best regards,

    Max