TLK2211 clock jitter spec

Orikasa,

Actually this is not an issue of lot to lot variation.  It really has to do with the frequency components of the jitter in the reference clock.

Maximum allowed jitter for TLK devices is specified in Peak-to-Peak (PP) value. For 40ps PP jitter, this means the absolute deviation in position of any rising edge is no more than 20ps away from the ideal position of the rising edge.

Now in practice, we can tolerate much more jitter than 40ps peak-to-peak max on the reference clock under certain conditions. High frequency (like cycle-to-cycle jitter) can violate the 40ps max datasheet spec, and almost no degradation would occur. Low frequency wander of many hundreds of ps would be okay if the customer doesn't mind low frequency wander in the data stream. This is usually the case because the receiver will track out the low frequency wander anyway.

 It is reference clock jitter around the bandwidth of the PLL that is really the concern. As an example, the bandwidth of the TLK12xx is in the neighborhood of 10MHz. Jitter components of the reference clock near the bandwidth of the PLL had better be under 40ps pk-to-pk or our output jitter performance will suffer. 

The customer often uses phase noise plots of the clock to determine the frequency components of jitter. I suspect that is the case of 400ps the frequency of the jitter is not around the bandwidth of the TLK2211 and there seems OK.  The only way for the customer to be sure is to look at the phase noise plots of their clock source.

Regards,

Atul