DP83TG720R-Q1: Clock Output Issue

Cui Xinglong

Prodigy 20 points

Part Number: DP83TG720R-Q1

Tool/software:

For Enable PHY Output 125MHZ Clock, I write the value of address 0x453 to 0x21 for enable the clock output.

I want to know

1. the clock is need PLL lock or not?

2. If the voltage is unstable, i enable the clock output, it will influence the clock accuracy and stable or not?

3.After I enable the clock output, i need wait a moment in the software then continue the init sequence ,the communication is normal. but if don't wait, will have some data lost.

Can you give me some good suggestion? Thanks

3 months ago

0 David Creger 3 months ago

TI__Mastermind 27222 points

Hi Cui,

125Mhz is based on the 25Mhz input crystal clock. Voltage must stay within the recommended operating conditions for clock output and device to function correctly.

Can you please share what this 125Mhz clock is being used for?

Thanks,

David

0 Cui Xinglong 3 months ago

Prodigy 20 points

HI，It's used for base clock for our MCU eth module running

0 David Creger 3 months ago in reply to Cui Xinglong

TI__Mastermind 27222 points

Hi Cui,

Register configuration is required to enable 125Mhz clock as PHY output. Likely the MCU is expecting 125Mhz to be available immediately, hence why the delay is needed to avoid data lost.

The best solution is to use a discrete 125Mhz clock generator to supply the MCU, instead of PHY output.

Thanks,

David

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DP83TG720R-Q1: Clock Output Issue