LMH0341: Regarding SDXILIP — Xilinx Spartan Example Code

Hi,

What is the input video clk frequency you are sending to LMH0341? Can you also physically measure the LMH0341 RXCLK frequency, are you seeing 74.25MHz or 148.5MHz?

Thanks

David

Hi David,

Well, On physical measure, LMH0341 RXCLK frequency is 148.5 only which is same as the frequency, that i am able to decode from the provided code. However, I am providing the 74.25MHz frequency as the PCLK for generating the HD-SDI output which is further feeded to LMH0341, and hence 74.25 is what i was expecting to receive as LMH0341 RXCLK frequency. 

Hi,

The RxCLKOUT is DDR. If divide by 4 is enabled, the output clock period will be doubled.

Can you please read LMH0341 register 0x28, bit 5 RXCLK Rate?

Thanks

David

Hi David,

I will test it and get back to you with outcome.

Hi David,

1. If the 0x28 bit 5 has value 1, which at the end providing me the double of the input frequency, can you please let me know if it will create problem in decoding image data using your code?

2. If i am further using the code to decode the format, In descrambling part, it is not able to satisy the 3 conditions of signal 'e', so, i want to know if this code can decode SMPTE ST 292M or some modifications are required for it.

Hi,

The LMH0340 FPGA codes support SMPTE259M, SMPTE292, and SMPTE424. The FPGA code was developed by the 3rd party, and my expectation is that the code is expecting to see 74.25MHz clock and will not support 148.5MHz clock. Have you verified the register 0x28 bit 5 value, is it 0 or 1?

Thanks

David 

The bit 5 of register 0x28 is 1.

As you are mentioning, LMH0340 fpga code supports SMPTE292, Is this code not applicable for LMH0341?

Hi,

This is typo on my part. The FPGA code is also applicable for LMH0341.

Thanks

David